On-Demand Web Seminar: Advanced UVM Debugging

Who Should View

What You Will Learn


As designs continue to grow in complexity, the testbenches to verify those designs are growing right along with them. A recent study shows that, on average, verification engineers spend more time on debug than on any other task, including creating and running the tests. The use of UVM and SystemVerilog to create object-oriented testbenches has magnified the need for a good debugging solution to allow engineers to focus on verifying the design, not fixing problems in the testbench. This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.