On-Demand Web Seminar: Verifying Complex SoC Designs with Questa Codelink

Who Should View

What You Will Learn


Verifying multiple blocks of design IP and achieving coverage closure is challenging enough. But verifying an entire SoC, with processors, memory, busses, and peripherals can be an enormous challenge, often involving a combination of simulation and emulation. This session shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments.