On-Demand Web Seminar: Debug Productivity with Questa: Introduction to advanced debug features in Questa for SystemVerilog class-based TB, OVM/UVM, and hard to find problems in RTL

Who Should View

What You Will Learn

An introduction to:

Overview

No one argues that today’s designs are rapidly growing in both size and complexity. Often IP is brought together from multiple sources (both internal and external), and can involve multiple design languages. To increase productivity and quality, verification engineers are also adopting advanced techniques and methodologies such as ABV(Assertion Based Verification)and OVM/UVM (Open/Universal Verification Methodology) and using languages such as SystemC and SystemVerilog. This variation and complexity in the verification environment demands new automation and capabilities for effective debug.

With native support of VHDL, Verilog, SystemVerilog and SystemC, Questa has a rich set of debug technology and functionality to help diagnose problems and find bugs fast. This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced traditional RTL debug with process debug, waveform compare, transaction-level debug, source code tracing, schematic view, causality tracing, X-trace, and other productivity features.