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IESF 2013: Hardware Development

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Technical Session
  • Efficient Compliance with ARP-4754A and DO-297 for IMA Systems
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    TECHNICAL SESSION Any new aircraft program that involves an Integrated Modular Avionics System will need to comply with SAE ARP-4754A, Guidelines for Development of Civil Aircraft and System and RTCA DO-297, Integrated Modular Avionics (IMA) Development Guidance and Certification considerations. As there are significant overlaps between these standards, an integrated certification approach is necessary to minimize the effort associated with compliance. This presentation will provide an introduction to efficient compliance with both standards.

Presenter: Marty Gasiorowski, FAA DER and President, Worldwide Certification Services
  • FPGA Design from Concept to Implementation to Safety/Mission/Security Success
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    TECHNICAL SESSION The design regulations for FPGAs and ASICs in commercial and military aircraft are some of the strictest to adhere to and for good reason – failure of electronics in commercial aircraft can have catastrophic results! While the commercial air industry has mandated the DO-254 hardware design standard, military aerospace companies are adopting design processes similar to DO-254, some even having their own auditors. By taking a design approach that is requirements-driven and well integrated for FPGA and ASIC design creation through device implementation, an excellent design process can be followed that will enable meeting the compliance needs of DO-254 and other such regulations, while also improving the project’s efficiency, productivity, predictability and final chip quality. This session will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

Presenter: Valerie Rachko, Director of Marketing, Mentor Graphics
  • HW and SW Design Demands Parallel Development
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    TECHNICAL SESSION Complexities and quality requirements of FPGA and ASIC designs today are demanding new design approaches that start with creation. The level of design abstraction must now be raised above RTL in order to contribute an entire new dimension of benefits to design, especially for multi-core architectures. Raising the design description language up from RTL to electronic system level (ESL), which is TLM-based (transaction level modeling), enables more design to designed, explored, validated, and co-designed with corresponding software and firmware using virtual prototypes to result in faster design cycles, higher quality projects, and higher levels of hardware and software design assurance.

Presenter: Jon McDonald, Strategic Program Manager, Mentor Graphics
  • Requirements Management: Ensuring Functionality and Accountability
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    TECHNICAL SESSION Requirement management and traceability is essential for safety-critical design processes used within the development of aerospace or military projects. This session explores how to manage and automate requirements traceability from specification through design, implementation, and verification. This session will detail key capabilities, including impact analysis and report generation, and take a look at capabilities to help manage requirements at a system level. This session will also describe how requirements tracking fit into a team environment and how one can trace requirements throughout many different tools and engineering flow

Presenter: Valerie Rachko, Director of Marketing, Mentor Graphics
  • Static Formal Verification Methods and their application to safety critical and military designs
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    TECHNICAL SESSION Today's complex electronic designs contain many behaviors that are difficult or even impossible to fully verify using conventional simulation-based verification techniques (For example, complex control logic, error recovery circuitry, Single Event Upset detection and correction logic, internal storage elements such as FIFOs, and many others). Verifying these types of design behaviors using simulation can lead to extremely long (and expensive) design verification tasks. Furthermore, even after "completing" the verification task, the design in question might not behave properly under all circumstances. It's common knowledge that bugs left in any design can be problematic, but for certain types and classes of designs, design errors are simply intolerable, especially if they are contained in satellites (where repair is intractable), safety critical designs (where bugs could cause injury or death), or military designs (where errors could place our military personnel or innocent bystanders in mortal peril).

    Luckily, there are alternative approaches that can be used to verify design correctness that are significantly faster and more thorough than traditional simulation-based verification. One such technique is Static Formal Verification (also known as "Model Checking"). Static Formal Verification is a technique that utilizes a mathematical analysis of the synthesizable digital design, and creates an unequivocal proof that the design behavior in question is, indeed, 100% correct – or it will prove that the design is NOT correct (i.e. It contains a bug), and will provide a waveform trace demonstrating the failure. This analysis is exhaustive, covering all input conditions across all time. When a design MUST be correct, and extremely thorough or exhaustive verification is needed, then Static Formal Verification is obviously a good technology to have in your tool belt. Static Formal Verification has a very strong pedigree. Many companies have used it for more than 15 years, and its popularity is growing rapidly thanks to IEEE design and verification standards.

    This presentation will discuss the use of Static Formal Verification, what it is and how it works, as well as the types of design behaviors where it is most and least effective. It will also discuss limitations and caveats, and provide links to papers and presentations containing more detailed information.

Presenter: David Landoll, Engineered Solutions Group, Mentor Graphics