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IESF: Network Design Integration AUTOSAR & Ethernet

Learn more about the latest tools and innovations for Network Design Integration AUTOSAR & Ethernet at IESF 2015 - Dearborn, MI, USA – May 19th, 2015.

Highlights include dedicated breakout track, case studies and solution demonstrations in the product area; plus a new feature this year – panel discussion!

F = Full registration required

Panel
  • Panel: Network Design, Integration and AUTOSAR
Technical Session
  • AUTOSAR: Vehicle Network Timing Analysis
    Toggle Abstract

    TECHNICAL SESSION Designing and implementing timing strategies for AUTOSAR-based vehicle networks has to take into account multiple network types, safety considerations relating to message delays, and the ability to test and predict performance of the entire network.  This session will look at the timing models of CAN and FlexRay vehicle networks, some of the design and analysis tools available to analyze and predict message transfer performance, and synthesize message frames.

Presenter: Tibor Kovacs, Mentor Graphics
  • Ethernet Backbone - Paving the Way towards Guaranteed Timing Behavior
    Toggle Abstract

    TECHNICAL SESSION Designers have become quite familiar with setting up vehicle network communication systems for CAN, LIN and Flexray networks, but how will the timing performance be verified in an Ethernet network? Ethernet is increasingly being used in areas such as vehicle network backbones, AVB MultiMedia systems, and DOIP diagnostics where high-bandwidth and reliable performance are essential. Accurate ECU timing performance prediction is critical to meet the requirements of ISO26262 for different ASIL levels. This paper will look at network-wide timing analysis challenges, where a mixture of CAN, FlexRay and Ethernet based network busses will co-exist. The AUTOSAR standard supports timing definition for all elements in such a mixed-topology network, but accounting for many possible different timing paths in a real-life network is a non-trivial process. Typically tens of thousands of signals are involved and each one may pass through several network gateways. Design Automation is an essential part of the process, and the benefits of using worst-case timing analysis, and predicting bus-capacity, while taking into account performance of different networking standards such as Broad-R Reach will be considered. A real-life example based on a Freescale ECU evaluation board will be used to illustrate the paper, along with Mentor Graphic’s own network analysis tools.

Presenter: Andrew Patterson, Director of Business Development, Embedded Systems, Mentor Graphics
  • Guest Presentation