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Mentor Forum 2014: DFT Tech Day

Hybrid Compressed ATPG and Logic BIST

Learn why reduce area overhead and tester patterns is driving interest in combining compressed ATPG and Logic BIST technologies to get the best of both worlds.

Mentor Forum
seminar

There are currently no dates scheduled for this event.

Overview

Over the years, deterministic ATPG and Logic Built-In Self-Test (BIST) have been seen as competing DFT technologies for manufacturing test. Each technology provides advantages and disadvantages in terms of test quality, test cost, and ease of use. For manufacturing test, compressed ATPG is the technology of choice for the vast majority of designs today but there are a small number of designs which implement Logic BIST only. The safety requirements for automotive (i.e. ISO 26262), the security needs for some consumer applications and the pin limitation of some applications have caused DFT engineers to look at Logic BIST as a suitable solution. Now, the need to reduce area overhead and tester patterns is driving interest in combining compressed ATPG and Logic BIST technologies to get the best of both worlds.

This seminar will explore the motivations, the concepts on these topics and introduce Mentor Graphics’ hybrid compressed ATPG and Logic BIST solution which provides the benefits of both technologies using smaller combined hardware.

What You Will Learn

  • Industry trends and challenges in manufacturing and in-system testing
  • Motivation and benefits of compressed ATPG and logic BIST methodologies
  • Overview of combined hardware for compressed ATPG and logic BIST
  • Overview of Mentor Graphics solutions for effective testing and yield improvement

About the Presenter

Jay Jahangiri

Jay Jahangiri is a Technical Marketing Engineer with Mentor Graphics' Silicon Test and Yield Analysis Solutions division. Prior to joining Mentor Graphics, he worked as a DFT engineer for Texas Instruments and Raytheon.

Jay holds a BSEE, an MBA, a US patent on reduced pin count test and has published numerous papers and articles in the area of silicon test.

Who Should Attend

  • Engineering managers responsible for manufacturing test costs and outgoing product quality levels
  • DFT and Test Engineers responsible for the generation and/or application of manufacturing test patterns

Products Covered

Agenda

Formal agenda starts at 10am.  Program will end after a complimentary lunch at 2:30 pm.

  • Product trends and DFT Challenges
  • Motivation for ATPG and Logic BIST
  • Mentor Graphics Hybrid ATPG and Logic BIST solution
  • Case Study examples

“The Tessent hybrid methodology is one of the most effective ways to reduce test cost and test time for IC products that require very thorough testing on the production line, as well as self-test capabilities after being placed into service.”

Joseph Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics.

 
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