Sign In
Forgot Password?
Sign In | | Create Account

Agenda

Print This Schedule

Thursday, October 16

Thursday, October 16

8:15 AM - 9:00 AM  1 session

  • REGISTRATION
    Toggle Abstract

    LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

ALL DELEGATES

9:00 AM - 9:10 AM  1 session

  • WELCOME
ALL DELEGATES

9:10 AM - 10:00 AM  1 session

  • EDA’s Key to Success: Riding Waves of Innovation
    Toggle Abstract

    KEYNOTE EDA must continually ride the waves of design innovation, solving design issues as they emerge. Being the first to develop a solution for a new problem is a win-win for both designers and EDA. The customer gets the tools needed to gain a competitive edge while the EDA company is rewarded with a leadership position in an emerging market. The best way for EDA to identify new design challenges is to partner with cutting-edge customers: whether they are large established companies, startups or companies in promising new markets or global regions.

    Greg Hinckley, President of Mentor Graphics, will discuss Mentor’s successful formula for identifying emerging design trends and creating world-class products for them. He will highlight recent product innovations that address such pressing concerns as IC physical verification and lowering the cost of IC test while expanding its reach into the cell level. Then, Mr. Hinckley will look at the biggest challenge on EDA’s horizon today—verifying the critical interactions between electronic hardware and the larger system design. Multifaceted approaches will need to be developed that encompass software, mechanical, thermal and stress as well as IC and hardware design.

ALL DELEGATES

10:00 AM - 10:15 AM  1 session

  • MORNING BREAK
ALL DELEGATES

10:15 AM - 11:15 AM  3 sessions

  • Introduction to the Analog FastSPICE (AFS) Platform
    Toggle Abstract

    TECHNICAL SESSION The latest addition to the Mentor analog/mixed-signal simulation and verification family is the Analog FastSPICE (AFS) Platform developed by Berkeley Design Automation (BDA), now part of Mentor. This session provides details on the AFS Platform, the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 16nm/14nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large analog/mixed-signal circuits, the AFS Platform delivers greater than 10M-element capacity and the fastest mixed-signal simulation. For silicon-accurate characterization, it includes the industry’s only full-spectrum, device noise analysis and delivers near-linear performance scaling with the number of cores. Come hear what Analog FastSPICE can do for your analog/mixed-signal design and verification flow

Products: Analog FastSPICE (AFS) Platform
Custom IC & Digital Design and Verification
  • Keynote: Navigating the Perfect Storm: Verification Challenges and Solutions
    Toggle Abstract

    TECHNICAL SESSION Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over 120. In the same period, the average number of embedded processors found in an advanced SoC increased from one to as many as 20. Beyond this growing functionality phenomenon are new layers of requirements that must be verified, such as multiple asynchronous clock domains, interacting power domains, security domains, and complex HW/SW dependencies. Add these challenges and many others together, and you have the perfect storm brewing. This talk introduces today’s trends and challenges in SoC design and verification and outlines Mentor’s vision for navigating this “perfect storm” of adverse challenges

Functional verification for FPGA & SoC
  • Keynote: Achieving Design Effectiveness
    Toggle Abstract

    TECHNICAL SESSION A design process optimized for speed often just means more ECOs; true effectiveness is achieved with speed AND quality. Quality is achieved by adhering to constraints throughout the design process to produce correct-by-construction designs. Quality also means incorporating a virtual prototyping process that optimizes manufacturability and performance of the end-product. This session will identify critical quality challenges, and an effective design process to address them.

Products: Xpedition VX
PCB Design to Manufacture

11:15 AM - 12:15 PM  3 sessions

  • PyxisOpen — assisted automation for the toughest Custom IC design problems
    Toggle Abstract

    TECHNICAL SESSION Mentor is bringing revolutionary insight and automation to the most intensively manual portion of custom IC design with PyxisOpen’s new OpenAccess (OA) based automation core. Learn how our interactive custom router boosts productivity as it shortens routing time by 10X and cuts weeks off tapeout schedules.

Products: PyxisOpen
Custom IC & Digital Design and Verification
  • Questa: High-Performance Simulation, Emulation and much more
    Toggle Abstract

    TECHNICAL SESSION With the growing size, complexity and software content of today’s SoC designs, verification requires a platform that gives you more than just simulation. Come see how Questa ties simulation, formal and emulation together and brings testbench automation, coverage closure, low power, abstract portable stimulus, new system-level metrics and more to maximizes your verification productivity.

Products: Questa 10.3
Functional verification for FPGA & SoC
  • Design Creation with Xpedition xDX Designer
    Toggle Abstract

    TECHNICAL SESSION xDX Designer delivers the Industry’s highest productivity by combining leading edge technology with extensive design automation and is very easy to use. This session will demonstrate the continuous evolution that was accelerated with the 7.9.4 release and exponentially increased by the significant enhancements in the VX.1 Release.

Products: Xpedition VX
PCB Design to Manufacture

12:15 PM - 1:15 PM  1 session

  • LUNCH
ALL DELEGATES

1:15 PM - 2:15 PM  3 sessions

  • Beyond verification: design productivity with Calibre RealTime and Calibre interfaces
    Toggle Abstract

    TECHNICAL SESSION Calibre provides the standard for verification engines. Getting to “done” requires that those engines work with your design flow and your design tools. We will show you how to maximize design productivity with Calibre interfaces into your design tools at every stage of design for both interactive verification with Calibre RealTime and batch verification with Calibre Interactive and RVE. We will also show you how Calibre DESIGNrev can save you hours of time in your design and verification flows. Get done faster with Calibre.

Products: Calibre Realtime, Calibre DesignRev, Calibre RVE
Custom IC & Digital Design and Verification
  • Visualizer: a powerful debug environment for complex SOCs
    Toggle Abstract

    TECHNICAL SESSION This session will focus on improving debug productivity with Visualizer, Mentor’s NEW high performance and capacity debug environment. Visualizer is tightly integrated with both Questa simulation and Veloce emulation to improve debug productivity for RTL, gates and SV/UVM testbenches. Visualizer is fast and intuitive with powerful, automated features that help pinpoint the cause of errors and explore your design.

Products: Questa Visualizer, Veloce
Functional verification for FPGA & SoC
  • Xpedition xPCB Layout
    Toggle Abstract

    TECHNICAL SESSION Xpedition PCB Layout is a real game changer. Optimized user interface, placement and planning tools, routing automation … all new technologies that will make Xpedition Layout easy to use for everyone and increase your productivity by an order of magnitude. Learn during this demonstration how quickly you can learn and adopt these innovations as part of your maintenance upgrade. Xpedition VX also delivers a complete 3D layout environment, including libraries and library management, tools, processes and standard interfaces with MCAD for importing parts or exporting board models. Learn during this demonstration how this complete environment takes electromechanical design in 3D to the next level.

Products: Xpedition VX
PCB Design to Manufacture

2:15 PM - 3:15 PM  3 sessions

  • Improving circuit reliability with Calibre PERC
    Toggle Abstract

    TECHNICAL SESSION Circuit reliability continues to be a focus for all process nodes. Verification techniques that extend beyond traditional DRC, LVS and ERC checks are needed to meet the demands of today’s designs. Device and interconnect reliability solutions that are scalable across many designs without the need for manual intervention improves the repeatability and efficiency of these checks. Come see how we leverage unique technology with foundry-provided rule decks to solve some of the most challenging reliability concerns IC designers face. We will also discuss electrical overstress (EOS), current density and electromigration issues, to name a few, which can be solved by the comprehensive Calibre PERC reliability verification platform.

Products: Calibre PERC
Custom IC & Digital Design and Verification
  • How to Accelerate Verification with 5 Easy to Use Formal Apps
    Toggle Abstract

    TECHNICAL SESSION What if you could harness the benefits of formal verification without the pain? That’s exactly what Questa’s fully-automatic formal apps allow you to do. This session presents the top 5 apps used to get better quality designs out the door faster. We’ll review apps for: (1) Clock-domain crossings, (2) Common RTL coding errors, (3) X-states, (4) Coverage closure, (5) Property generation

Products: Questa
Functional verification for FPGA & SoC
  • Valor NPI - Integrated DFM
    Toggle Abstract

    TECHNICAL SESSION Ensuring that your PCB designs are optimized for manufacturing just got a lot easier with Valor NPI technology embedded in the desktop of the Xpedition VX release. Valor Fabrication DFM checks can be run by the Xpedition designer at any stage of the layout process, entirely from within the Xpedition user-interface. The latest version of Valor-NPI completes the design validation and final preparation of the manufacturing data for hand-off to fabrication, assembly and test process engineering. You will see how the combination of full DFM analysis before manufacturing handoff plus the use of the new version-8 ODB++ data enable fastest transition to volume manufacturing across multiple manufacturing suppliers.

Products: Valor NPI
PCB Design to Manufacture

3:15 PM - 3:45 PM  1 session

  • AFTERNOON BREAK
ALL DELEGATES

3:45 PM - 4:30 PM  3 sessions

  • Parasitic Extraction to Meet the Challenge of Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION The world is 3D! Leading edge designers are considering new designs at advanced process nodes with 3D transistors (FinFETs). Others are considering “More than Moore” and opting for a 3D-IC approach. Everyone wants more accuracy which implies 3D modeling techniques to achieve high correlation against reference results. With these new challenges come traditional concerns of turn-around time (TAT), growing design complexity, double-patterning and growing number of interconnect corners that add to the challenge of robust parasitic extraction. This session will describe how new methods in Calibre have been developed to address these challenges and meet the performance, accuracy, and usability concerns for designers at all nodes.

Products: Calibre nmLVS, Calibre xACT
Custom IC & Digital Design and Verification
  • Maximize Verification Reuse with Portable Stimulus
    Toggle Abstract

    TECHNICAL SESSION Verification productivity and reuse are of key concern when verifying today’s complex designs. The ability to rapidly create large amounts of comprehensive test sequences at block, subsystem, SoC and system level are key to ensuring design quality. One key obstacle to achieving comprehensive testing today is the lack of a consistent stimulus specification that is reusable from block to system level. Recently, in response to industry demand, the Accellera Systems Initiative board launched a proposed working group to investigate whether to standardize a portable stimulus specification. This session will show how a portable stimulus specification brings 10-100x faster coverage closure to block level verification, and reusable comprehensive tests to SoC and system level verification

Products: Questa inFact
Functional verification for FPGA & SoC
  • Optimizing Systems Performance with Electrical Sign-off
    Toggle Abstract

    TECHNICAL SESSION Nearly all system designs have some sort of electrical performance flaws when first created. Finding and quantifying the severity of these design flaws at the PCB level remains a big challenge for design teams, especially for highly constrained designs. This session presents a better way to manage the electrical sign-off (ESO) process to help achieve first time electrically-correct PCB design. The ESO design practice described here leverages HyperLynx to perform full-board screening as well as detailed 2D/3D analysis to validate performance.

Products: HyperLynx
PCB Design to Manufacture

4:30 PM - 5:15 PM  3 sessions

  • Update on DFM and Fill for Advanced Nodes
    Toggle Abstract

    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
Custom IC & Digital Design and Verification
  • Full SoC emulation from device drivers to peripheral interfaces
    Toggle Abstract

    TECHNICAL SESSION Companies have added a tape out requirement that ensures their SoC executes the OS loader to a boot prompt. Thus, verification of HW/SW interactions is no longer just a good idea, it’s a hard requirement. The methods for executing and debugging OS boot and device driver software on hardware during emulation are evolving rapidly. This session contrasts live versus off-line SW debug tools in the context of multi-core SoC designs, and physical versus virtual peripheral models as device driver targets. Participants will come away with an understanding of how an emulation-based, end-to-end flow yields a higher confidence at tape out and a faster time to market.

Products: Veloce
Functional verification for FPGA & SoC
  • HyperLynx DRC - Powerful, fully customizable and fast DRC tool
    Toggle Abstract

    TECHNICAL SESSION What are you doing for electrical signoff? The HyperLynx family of solutions offers the best coverage for your SI, PI, and EMI and thermal issues with uncompromising accuracy and industry recognized ease of use. HyperLynx DRC allows not only the SI engineer, but the PCB Designer as well, to quickly and reliably validate your designs against a limitless range of design guidelines and best practices so that weaknesses can be identified before simulation takes place. See how recent usability enhancements further reduce the learning curve for every user, and how integration with the data management flow helps to ensure that you perform your analyses using the latest collateral.

Products: HyperLynx
PCB Design to Manufacture

5:15 PM - 5:30 PM  1 session

  • CLOSING COMMENTS
ALL DELEGATES