Agenda

LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

TECHNICAL SESSION Winning products are rarely the result of optimizing only one aspect of a design. Innovators generate success because they find ways to cross organizational and functional boundaries to optimize a product in multiple disciplines. Mature companies try to solve this problem by creating cross-disciplinary teams while startup companies do it naturally due to lack of enough resources to allow specialization. Meanwhile, products targeted at customers in different disciplines rarely appeal to more than one. Dr. Rhines has compiled data on cross-disciplinary product successes including attempts by companies to create products for hardware/software co-design, mechanical/electrical design integration and many more. He has identified successes and categorized the ways that companies have (rarely) achieved multi-disciplinary product optimization. He will use these examples to generate some guidelines for companies of all sizes to achieve product development success.

TECHNICAL SESSION Recent industry surveys show that two-thirds of new design projects fall behind schedule due to verification.  In addition, 70% of these designs fail at least once after verification is completed.  With over half of these failures attributable to logic and functional errors, it makes sense that coverage closure is consistently identified as one of the most difficult challenge faced by verification teams. This session will how Questa can help to gain 10X to 100X in verification productivity by automatically generating SystemVerilog cover groups and Clock Domain Crossing coverage models, reducing nightly regression setup time, automating results merging and coverage analysis and intelligently generating stimulus that achieves target coverage closure faster, and increases overall coverage.

TECHNICAL SESSION As product complexity has increased, organizations have been under constant pressure to meet their business drivers while bringing competitive products to the market-place. These pressures are being compounded by a significant demographic shift in heritage PCB design and engineering. In the western world, new entrants into the PCB design workplace is in decline, this is happening when engineering graduates as a whole are also in decline. Meanwhile, products are becoming more complex where, what was once isolated processes are now very much integrated. To ensure the viability of the next generation of engineering, there is a drive to lower the barriers to perform core engineering and design activities while enabling organizations to take a systems approach in their development strategies. This keynote will cover these trends and introduce Mentor’s view of integrated systems design for an industry in transition by showcasing specific technologies that will enable next generation of PCB development.

TECHNICAL SESSION Attend this session for an overview of the physical verification, DFM, and extraction solutions being offer by Mentor. The session will highlight the latest features of the Calibre platform and how they are being used by foundry and IP partners to address the issues encountered by designers, including both 2D chip scaling and 3D stacking approaches. The session will also show you how to use Calibre in your design flow to achieve a single sign-off solution regardless of the P&R and custom layout flows or the foundry process you have selected.

TECHNICAL SESSION The adoption of Formal Verification technology has traditionally been encumbered by performance, capacity and ease of use issues. With the Questa Static solution complete SoC designs, greater than 150M gates in size, can now be analysed in a single step. Tens of thousands of assertions for multi-million gate design blocks can now be proven in a matter of hours. Huge strides have been made in advancing the usability of the formal tools, with the development of new features and refinement of methodologies, so that this ground breaking power has been brought to a whole new level of automation. In this session will discuss how to eliminate the risk of metastability issues in silicon, automatic formal checks for push-button checking to find functional issues, formal code coverage closure to prune unreachable bins from the coverage model, static X-propagation verification to verify that X-optimism is not masking design bugs and connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections.

TECHNICAL SESSION PCB systems complexity is increasing at almost an exponential rate. To leverage technology advances and create more competitive products while meeting productivity and time to market goals, requires advanced design technologies as provided only by Mentor Graphics. This session will illustrate some of those technologies such as BGA breakouts, advanced routing, power distribution network design, large system design definition and work-in-progress design data management.

TECHNICAL SESSION In complex analog design and at advanced nodes, ICs are more sensitive to electrical overstress (EOS) failures and require additional checks that cannot be performed using standard solution as DRC, LVS or ERC. IC designers need new techniques to validate that all required protection structures are in place, and that the complex and special design rules are met. In this session we will describe a Power Management technology, complex design rules as well as its ESD objectives and challenges, and how it is using Calibre PERC to increase the quality of design and improve long-term reliability. A case study will describe the techniques used, how checks were developed in Calibre PERC and the results achieved.

TECHNICAL SESSION As the saying goes, “if you fail to plan, you plan to fail.” The same is true of a verification project, where establishing a verification plan up-front is critical to your overall success. Starting with requirements, a verification team must be able to create an environment aimed at verifying that the design meets all of the requirements accurately. That involves designing stimulus, monitoring behaviour and recording results, as well as managing the resulting data, using proper tools and techniques to turn those data into useful information, and closing the loop to correlate that information against the original requirements. This session will discuss the Verification Management features of Questa, which allow you to collect, categorize, analyse and triage your verification results to ensure that your verification coverage goals have been met, and that your verification infrastructure is being used to its maximum efficiency to achieve verification closure.

TECHNICAL SESSION The design of complex PCB systems requires the coordinated efforts of extended design teams as well as leveraging the Intellectual Property of the company such as component libraries and re-usable designs. This requires data management infrastructure that is specifically tuned to the PCB design process. This session will illustrate Mentor's successful capabilities in this area.

TECHNICAL SESSION Today’s complex system development programs often struggle with late stage problem awareness, which can arise from document-based processes, isolated development teams, and verification done far too late in the process. Managers also have to deal with the skill sets and flexibility of their people, the tools they use, and how to capture and reuse their knowledge. This session presents an innovative system and design team integration capability featuring SystemVision, Mentor Graphics’ solution for modelling, simulation and analysis of systems from conceptual level mechatronics down to the boards that implement them. SystemVision is a multi-discipline virtual prototyping “lab” environment that enables powerful verification and collaboration across disciplines (including analog, digital, mixed-signal hardware, software, controls, and mechanical aspects), in an integrated design environment. This session will introduce SystemVision in the context of how its being used across a spectrum of Systems development programs in automotive, aerospace, defence, medical and industrial industry segments.

TECHNICAL SESSION As many design teams can attest, fast emulation has become a critically important verification component for large and complex systems-on-chip (SoC's). Today, emulation is used to test the hardware aspects of a SoC design and to verify the integration of hardware and the embedded software. It is possible to start RTL verification at the block level and move on to the system level as the entire design takes shape. Emulation can also co-verify the interaction of hardware and software once the full RTL design is complete. In this session, learn about the latest and greatest for the Veloce platform and it’s non-intrusive, software based application’s environment “VirtuaLAB” .

TECHNICAL SESSION Not only are speeds of systems increasing rapidly and now in the multiple Gbps, but the percentage of high speed nets common at over 75%. This all requires extensive analysis and verification during the design process versus producing physical prototypes and testing them in the lab. This session will discuss these required analysis tools in detail for signal integrity analysis of DDRx and SERDES interconnects, Power Distribution Network analysis, the inclusion of 3D SI analysis for via structures, and Analog simulation.

TECHNICAL SESSION This session provides attendees with Mentor's product vision, and in depth discussion about our market leading custom IC Design Flow tools. Attendees will receive an introduction and demonstration of our constraint driven custom analog router and Calibre RealTime on-demand signoff design rule checking. The session will conclude with a discussion of Mentor's long term roadmap and strategic technical direction including an update on support for OA based environments.

TECHNICAL SESSION SoC and System designs are reaching a breaking point with two key related challenges: complex multi-core architectures and software integration. Hardware design is now focused on integrating application, graphics and wireless and I/O sub systems that must be accompanied with proper software layers. This integration and verification effort of hardware architecture, drivers and operating systems, is critical for any silicon delivery, hence must be handled ahead of silicon tapeout. In this session, we will outline how virtual platforms, potentially combined with emulation, can address hardware prototyping, software bring up and system validation in pre-silicon phases, and how they can support performance and power analysis tuned to realistic use cases and real-time applications.

TECHNICAL SESSION Poor reliability of a product can lead to extensive warranty cost, product recalls and bad reputation. There are many causes of poor reliability such as excessive heat, vibration and shock, marginal manufacturing, and poor power distribution network design. This session will discuss how virtual prototyping analysis can predict long term reliability issues and help designers eliminate them without the use of expensive and time consuming physical prototypes and test chamber testing.

TECHNICAL SESSION Come see what differentiates our full SPICE, Faster SPICE or Fast SPICE high performing simulation solutions including, smart Monte Carlo, sensitivity and aging analysis and optimizations for the fastest, most accurate cell characterization. We will also present an updated roadmap and the new features added in recent releases.

TECHNICAL SESSION Leveraging FPGAs in your system allows you to bring products to market much faster than using ASICs or custom ICs.  However, unless you properly manage the complete development flow across the FPGA and PCB domains, you may encounter delays due to FPGA timing closure, FPGA functional validation, PCB routing challenges, and worst case—costly board re-spins. Greater system performance, reduced production cost, and first pass success are competitive advantages in most markets. This session will discuss how to develop an FPGA design methodology that balances performance, validation, cost, and schedule requirements.

TECHNICAL SESSION The engineering of a complex system of multiple PCBs by a team of engineers requires not only an advanced systems definition capability but also the ability of teams of engineers to define the system and the design constraints concurrently. This session will illustrate Mentor's technology that is unique in the industry where multiple engineers can work on the same schematic and define high speed constraints on a system concurrently while viewing their peers' edits real time. Also the ability to define the multi-PCB system top-down with automated backplane and cable integrity.

TECHNICAL SESSION This session explains how Questa ADMS extends digital verification across the analog/digital boundary with AMS debugging, dynamic performance/accuracy trade-offs, analog coverage, analog assertions, UPF and UVM. The UCDB coverage database integrates Questa ADMS in the comprehensive Questa verification management flow. We will also explain this can be combined with the Mentor Faster Spice and Fast Spice solutions (Premier and ADiT) to achieve full SoC mixed signal verification.