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Tuesday, October 01

Tuesday, October 01

8:00 AM - 8:50 AM  1 session

  • REGISTRATION
    Toggle Abstract

    LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

ALL DELEGATES

8:50 AM - 9:00 AM  1 session

  • WELCOME
ALL DELEGATES

9:00 AM - 9:45 AM  1 session

  • Keynote : THE BIG SQUEEZE
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    KEYNOTE For decades, we’ve known it was coming and now it’s here. Moore’s Law—which is really just a special case of the “learning curve”—can no longer drive the 30% per year reduction in cost per transistor, beginning with the 20/16/14 nm generation. Either we find innovations beyond just shrinking feature sizes and increasing wafer diameter or we slow our progress down the learning curve, introducing innovative new electronic capabilities at a slower rate than in the past.
    There are lots of alternatives, including a reduction in profitability of the members of the supply chain, to keep the progress continuing at the same rate as the last fifty years. Dr. Rhines will review the mathematical basis for the dilemma and, with his brand of humor, provide a roadmap of possibilities for the decade ahead.

Presenter: Dr Walden Rhines, CEO & Chairman of the Board, Mentor Graphics
ALL DELEGATES

9:45 AM - 10:00 AM  1 session

  • MORNING BREAK
ALL DELEGATES

10:00 AM - 11:00 AM  3 sessions

  • Questa 10.2 Update (GUI, Debug, VM, inFact, VIP & Power Aware)
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    TECHNICAL SESSION Questa 10.2 offers significant enhancements in verification productivity with performance improvements across the entire spectrum of engines and solutions, unified debug, leading verification management and analysis capabilities, and superior support of the latest methodology and language standards.
    Performance: The Questa 10.2 release delivers multiple performance improvements in simulation—up to 3X in designs using SystemVerilog/OVM/UVM, up to 5X with Questa Multi-Core Simulation, and up to 6X for Low Power simulations with UPF.
    Debug: Questa 10.2 introduces new technology that allows users to easily sync all analysis windows, track forward and backward in time, and automatically trace issues back to the original cause, dramatically reducing debug time and increasing productivity. For UVM and SystemVerilog users, the Questa 10.2 release has multiple new capabilities including a dedicated UVM window, UVM native objects in all the major debug windows, a Constraint Explorer, and UVM Register Assistant.
    Attend this session to get to know how Questa 10.2 can help yuo increase verrification productivity

Design & Verification of SoC & FPGA
  • Unleash the Full Power of your PCB Design Entry Software Tools
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    TECHNICAL SESSION The next major release of Expedition Enterprise will take your PCB Design Entry productivity to the highest level. Come and see how we are making the tool much easier to use for both casual and expert users alike. In addition, we are introducing a new leading edge floorplan-based technology for FPGA on-board optimization. Be one of the first to see live demonstrations of the new industry leading design entry technologies.

Products: DXDesigner, IODesigner
PCB Design & Analysis
  • High-Performance Cell Library Characterization and Validation
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    TECHNICAL SESSION At 45 nm and below, speed and power consumption are much more sensitive to environmental conditions, including voltage and noise. Producing accurate models at the appropriate conditions is critical to achieving design success. This session will cover how designers can quickly and easily generate accurate performance models for standard cells, I/Os, memories and complex cells.

Products: Kronos (Charaterization/Analysis)
Analog Mixed-Signal & Physical Verification

11:00 AM - 12:00 PM  3 sessions

  • Verification:  Automate When Possible
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    TECHNICAL SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!

Products: Questa Formal verification, Questa CDC verification, Questa covercheck
Design & Verification of SoC & FPGA
  • Improving Layout Design Productivity
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    TECHNICAL SESSION Layout design is increasing in complexity due to additional constraints on electrical performance and manufacturability. This session will highlight new technology coming to the Expedition flow for layout design. Key additions include automation of interactive sketch routes, a context-sensitive modeless environment, hierarchical placement, and many other improvements.

Products: Expedition PCB
PCB Design & Analysis
  • Pyxis Open – The New Era in Custom Design – Automating the CORE
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    TECHNICAL SESSION Mentor Graphics is bringing revolutionary insight and automation to the most manual portions of custom IC design – the core – routing, placement and floor planning. Hear how our revolutionary interactive custom router is changing the competitive game for its users as it shortens routing time by 10X’s and cuts weeks of our customer’s tape out schedules. Also enjoy a sneak preview of our next deliveries for the automation core.

Products: Pyxis Open
Analog Mixed-Signal & Physical Verification

12:00 PM - 12:45 PM  1 session

  • LUNCH
ALL DELEGATES

12:45 PM - 1:45 PM  3 sessions

  • Providing Coverage
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    TECHNICAL SESSION The first FPGA Verification session “Providing Coverage” describes code and functional coverage, and how each of these verification techniques can be applied to your verification process. Step by step adoption flows are presented. Answer questions about how coverage can improve FPGA lab productivity. What is the benefit of adding functional coverage? What is the impact of code coverage? How to deploy new processes and manage FPGA project demands. Why does coverage matter and how to leverage FPGA verification process improvements.

Design & Verification of SoC & FPGA
  • Multi-Board Systems Design
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    TECHNICAL SESSION The engineering of a complex system of multiple PCBs by a team of engineers requires an integrated set of tools from system-level functional block definition to partitioned PCBs. This session will introduce new technology that provides a single cockpit for all conceptual and logical system definitions, eliminating data re-entry errors and improving system performance.

Products: Systems Designer
PCB Design & Analysis
  • Calibre for Legacy processes
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    TECHNICAL SESSION Communciation around new features and advacned nodes always drive the crowd to the smaller ndoes available. This unfortunately hide the large variety of legacy nodes which are in production today and which also requires advanced techniques to ease the lfie of the designers or the fab engineer. We will concentrate on those so called legacy nodes which by the way are feeding our ecosystem. We will span the large variety of Calibre tools, batch and interactive which allows end users to eprform DRC/LVS checks, debug complicated issues, bring Calibre int eh design environment.

Products: Calibre nmDRC Calibre nmLVS Calibre OPCpro Calibre PERC Calibre Interactive Calibre RVE Calibre DesignRev
Analog Mixed-Signal & Physical Verification

1:45 PM - 2:45 PM  3 sessions

  • Improved Debug with Assertions
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    TECHNICAL SESSION The second FPGA Verification session “improved debug with assertions” provides a strong case for a step by step method for the adoption of assertions. All the sessions discuss steps for incremental adoption of assertions into your pre-lab verification process. Who is using assertions? What assertion languages and libraries they are using and why assertions add value. We also recommend where to place assertions, and an overview of how to apply them.

Design & Verification of SoC & FPGA
  • Enabling Enterprise Design Data Management
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    TECHNICAL SESSION The Expedition Enterprise flow is centered on a common design infrastructure between engineering teams, analysis tools and experts, PCB layout, production engineering, and the manufacturing floor. Managing the evolving design data in this environment can be very dynamic, with all of the above data continuously changing. The dynamics of an integrated flow have proven to significantly increase productivity, but also require integrated management of native design data and processes throughout the lifecycle of the design. The complexities of this integrated data set must be clearly understood to accurately move or bundle the design data, or downstream issues can occur and data can become out of sync — leaving you to wonder if you have the right data. We will introduce a new solution (EDM) that addresses both the WIP information management and design data management challenges. EDM provides a centralized environment to manage all the data required to conduct the ECAD design, facilitating collaboration among engineers in real time during the design phase.

Products: EDM (with maybe some DMS updates)
PCB Design & Analysis
  • Comprehensive Circuit Reliability with Calibre PERC
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    TECHNICAL SESSION Implementing a robust IC verification methodology that addresses circuit reliability is increasingly difficulty for all process nodes. Larger nodes are seeing new challenges that were not apparent in previous generations, such as increasing design complexity. Smaller nodes are seeing greater sensitivity to electrical overstress (EOS), current density and electro-migration issues. For designs with multiple complex power domains, transistor-level power intent verification can be difficult to verify, but new tools are emerging to automate such checking by leveraging UPF. This session describes how Calibre PERC can provide a comprehensive reliability verification platform to address these problems.

Products: Calibre PERC Calibre LVS
Analog Mixed-Signal & Physical Verification

2:45 PM - 3:15 PM  1 session

  • AFTERNOON BREAK
ALL DELEGATES

3:15 PM - 4:15 PM  3 sessions

  • Accelerating Coverage Closure using Intelligent Testbench Automation
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    TECHNICAL SESSION With the Questa functional verification platform, achieving coverage closure means much more than just generating stimulus and hoping for coverage results. Questa eases testbench programming by leveraging its robust Verification IP Library, automates the generation of coverage models, and intelligently generates stimulus to ensure that high test quantity does not come at the expense of high test quality. Questa also reduces the time needed to manage regression testing and merge coverage results from hours to minutes.

    Attend this session to learn how Questa can help you can gain 10X to 100X in verification productivity by
    • Automatically generating SystemVerilog covergroups and coverage models
    • Intelligently generating stimulus that achieves target coverage closure faster, and increases overall coverage
    • Reducing nightly regression setup time, and automating results merging and coverage analysis

Products: INFACT
Design & Verification of SoC & FPGA
  • Using Accelerated Techniques to Exhaustively Scan Whole PCBs for Potential Problems
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    TECHNICAL SESSION In spite of efforts to make detailed SI and PI simulation as productive as possible, today’s constricted design windows make it difficult to analyze the electrical performance of an entire PCB. How can a designer ensure that no problems “sneak through” into production versions of a board? HyperLynx addresses this need with several automated features requiring minimal modeling and setup, but offering fast verification techniques that make triage of an entire PCB practical. These include accelerated approaches to DC-drop, thermal, crosstalk, and decoupling-capacitor-mounting analysis. Of special note is the new HyperLynx DRC product, a powerful, rules-based verification solution capable of exhaustively analyzing a routed board for common signal-integrity, power-integrity, and EMI/EMC design-guide violations. Out-of-the-box, HyperLynx DRC can rigorously find violations of 22 detailed electrical checks; companies can also author custom rule sets (encrypted, if desired) tailored to proprietary design processes. The DRC product is an exciting addition to the HyperLynx product line — be sure to learn about its unique capabilities in this session.

Products: HyperLynx DRC, including standard and custom rules
PCB Design & Analysis
  • DFM at Advanced Nodes
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    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Products: Calibre LFD Calibre YE/YA/YS
Analog Mixed-Signal & Physical Verification

4:15 PM - 5:15 PM  3 sessions

  • Advanced methodologies: Reusing TB's from TLM to RTL with Questa and UVM Connect
    Toggle Abstract

    TECHNICAL SESSION This presentation introduces Mentor's open-source UVM Connect library and will show examples on how it can be used for advanced TB usage bridging TLM and RTL.
    UVM Connect enables the following use-models:
    Abstraction refinement - Reuse your SystemC architectural models as reference models in UVM verification as well as reusing your stimulus generations agens in SV to verify models in SystemC.

    Leveraging language strengths - You can leverage SV's powerful constraint solvers and UVM's sequences to provide random stimulus to your SC architectural models. You can leverage SC's simulaiton speed and capacity for verification of untimed or loosely timed system-level environments. We will present real live examples of how Questa and UVM Connect can help you with a truly mixed abstraction level verification environment.

Design & Verification of SoC & FPGA
  • High-Speed Design
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    TECHNICAL SESSION Virtual prototyping through simulation is critical for today's multi-gbps, SerDes, DDRx, low power designs. We will discuss the latest advances in our simulation tools for signal/power/thermal/EMI integrity, including validation studies that confirmed simulation accuracy at multi-gbps.   

Products: HyperLynx SI/PI/HL 3D with 9.0 and VX content
PCB Design & Analysis
  • Preparing for Pervasive Photonics
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    TECHNICAL SESSION Silicon photonics is using silicon for the fabrication of light-based devices—such as lasers, amplifiers, converters, filters and splitters. Current applications include ultra-fast chip-to-chip optical interconnects, optical routers and signal processors. Visionaries see SP as an enabling technology that will impact many facets of life through entertainment, medical discovery, communications, information storage, and manufacturing. This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that will SP open up, and new challenges it will present to IC designers.

Products: Calibre nmDRC Calibre nmLVS
Analog Mixed-Signal & Physical Verification

5:15 PM - 5:30 PM  1 session

  • CLOSING COMMENTS
ALL DELEGATES

5:30 PM - 9:00 PM  1 session

  • Networking and cocktail reception
    Toggle Abstract

    LOGISTIC Conference close will be celebrated with a cocktail reception offering relaxed networking time.

ALL DELEGATES