Mentor Forum India 2012: ESL & Functional Verification

Technical Session The adoption of Formal Verification technology has traditionally been encumbered by performance, capacity and ease of use issues.With the Questa Static solution complete SoC designs, greater than 150M gates in size, can now be analyzed in a single step. Tens of thousands of assertions for multi-million gate design blocks can now be proven in a matter of hours. Huge strides have been made in advancing the usability of the formal tools, with the development of new features and refinement of methodologies, so that this groundbreaking power has been brought to a whole new level of automation.In this session, we discuss five solutions offered with the Questa Static products that you can incrementally add to your design flow and that are must-have components in any complete verification flow:• Clock domain crossing (CDC) verification to eliminate the risk of metastability issues in silicon• Automatic formal checks for push-button checking to find functional issues without writing a testbench or assertions• Formal code coverage closure to prune unreachable bins from the coverage model• Static X-propagation verification to verify that X-optimism is not masking design bugs• Connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections

Technical Session As many design teams can attest, fast emulation has become a critically important verification component for large and complex systems-on-chip (SoCs). Today, emulation is used to test the hardware aspects of a SoC design and to verify the integration of hardware and the embedded software. Attend this session to hear how the Veloce platform provides high-speed emulation solutions for the verification of SoCs in a “virtual lab” environment. Each application is software-based, creating a non-intrusive environment that is reproducible, expandable, and available to share between multiple verification teams.

Technical Session The era of platform-based SoCs has arrived. By increasing the granularity of pre-integrated and reused IP within an SoC platform, subsystems allow faster design and delivery of platform-based systems. Reusable subsystems represent the next advancement towards ever larger, reusable design functions. However, with each step in the size of reusable blocks, the integration and system verification complexities expand exponentially, from limited parameterization to partial and full programmability. To realize the benefits of platform-based SoCs, users must be able to develop, optimize, integrate and verify differentiating hardware blocks and the software that defines the final system. Time-to-market and quality are keys to success. Software development and validation must begin on day one to avoid costly schedule delays. Multi-core platforms, with extensible coherent memory, increase the SoC architectural design, integration, verification, and debug challenges. Full system verification and test must begin early in order to adequately test the full breadth and depth of system architecture and performance and deliver the quality that today’s market demands. In this session, we will cover the process of defining an ARM-based design based on platform subsystem IP, the development and integration of hardware acceleration blocks, analyzing system performance criteria, verification of the SoC functionality, the development and validation of software using virtual prototyping and acceleration technology and verification from block to SoC to full system.

Technical Session With the explosion of consumer electronics, designing for low power has become an important design constraint and a key differentiating factor. In this session, Calypto will cover its two platforms for optimizing power across the entire SoC: 1) PowerPro Platform: Targeted at RTL designers who want to reduce power for legacy IP and existing RTL designs. The Power Platform is based on patented sequential analysis technology which allows PowerPro to looks across 100’s of clock and functional boundaries to find greater power savings. 2) Catapult LP (Low-Power) is targeted at hardware designers who want to use SystemC or C++ to optimize power at the architecture level using high level synthesis. Catapult LP is Calypto’s newest product announced May 29th, 2012 at the Design Automation Conference (DAC). Catapult LP takes advantage of Calypto’s unique PowerPro® technology by embedding it “under the hood” to optimize designs at the architecture level where 80% of power decisions are made. Come hear how Calypto’s proven technology can help you meet your low power goals.