Mentor Forum India 2012: IC Design & Test

Technical Session IC designs at 20nm will have new structures and new techniques that impact parasitic extraction. Designers will need new models for both local interconnect and device-level structures. They will also need efficient ways to handle colored vs. non-colored data for double patterning, and more extensive corner management. 3D-IC could also require a paradigm shift in how we represent traditional parasitics and new TSV models. This session will cover how the Calibre product line can address these critical challenges.

Technical Session Advanced fill is the next big challenge at leading edge nodes. Traditional dummy fill can no longer meet all the subtle requirements of advanced nodes, which go far beyond maintaining planarity during the CMP process. Mentor’s Calibre SmartFill solution is ready today to address advanced fill dependencies at 20nm such as Rapid Thermal Annealing (RTA), etch rates, stress and other factors. An intelligent fill solution meets the new requirements while delivering smaller post-fill GDS database size and faster runtimes without manual customization or modification. Come and learn about what is driving the new fill approaches and how Calibre SmartFill can meet the new requirements in your design flows.

Technical Session In complex analog design and at advanced nodes, ICs are more sensitive to electrical overstress (EOS) failures and require additional checks that cannot be performed using standard solutions such as design rule (DRC), layout vs. schematic (LVS) or electrical rule checking (ERC). IC designers need new techniques to validate that all required protection structures are in place, and that the complex and special design rules are met. In this session TowerJazz will describe its Power Management technology and associated complex design rules, as well as its ESD objectives and challenges. The session will also describe how TowerJazz is using Calibre PERC to increase the quality of design and improve long-term reliability. A case study will describe the techniques used, how checks were developed in Calibre PERC, and the results achieved.

Technical Session Delivering a correct, high yielding product on time becomes more and more difficult at each manufacturing node due to an increase in number and complexity of design-sensitive issues. This session describes how diagnosis-driven yield analysis (DDYA) accelerates time to root cause of yield loss and identifies yield limiters using statistical analysis of volume test diagnosis data in a way that augments traditional solutions. First, scan diagnosis determines the defect classifications and locations for each failing die, based on the design description, scan test patterns, and tester fail data. Second, specialized statistical analysis is used to identify and separate systematic yield limiters in seemingly random fail data and select the most suitable devices for failure analysis. The presentation will cover recent advances in diagnosis technology and diagnosis results analysis such as layout-aware diagnosis and DFM-aware yield analysis, as well as results from several industrial case studies.

Technical Session 20nm and 3D-IC bring significant changes to how designers must perform physical verification (e.g. DRC, LVS, PEX, Fill, etc.). Come learn about the challenges and how to prepare so that you can quickly ramp your next design to production. This is a one-time only, limited seating event for advanced Calibre users. Register today to reserve your spot.

Technical Session The growing adoption of 3D packages is driving the need for advanced test solutions. The good news is that many of the advanced Tessent® solutions developed for leading edge 2D designs are well suited for addressing new 3D test requirements as well. A critical requirement for ensuring acceptable 3D package yields is very high quality of the bare die going into the package. A proven approach to achieving this low defect per million (DPM) goal is the use of ATPG patterns generated using the Tessent cell-aware fault model based capability. The rapid adoption of memory stacked on logic applications requires new methodologies for testing the bare memories and their TSV connections to the base logic die. The Tessent MemoryBIST capabilities developed for addressing bussed internal ARM core memories as well as unique features for testing external DRAM memories are perfectly suited for testing stacked bare DRAM die. These capabilities and many other advanced features of the Tessent family of test products will be discussed in this session.

Technical Session Beginning at 20nm, the challenges of lithographic imaging require the use of double patterning techniques, which bring new requirements into the design and verification space. In this session we will take a deep dive into the requirements and discuss the methodologies and tool solutions you need to be successful at 20nm.

Technical Session With the advent of 20nm, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time they also face a slew of new design challenges at 20nm that severely impact design performance, power and time to market. Challenges such as double patterning aware placement and routing, DFM, extraction and timing, larger design sizes, stringent low power requirements and process variations have a major impact on design performance and productivity. This session will highlight some of the key capabilities and differentiators that Olympus-SoC offers to address complex 20nm challenges, and also provides a sneak peak of the product roadmap.