All Mentor Forum India Events

KEYNOTE The first keynote will be presented by Wesley Ryder, Mentor Graphics. As the Worldwide Technical Director of one of the “Big 3” EDA companies, Wesley will offer insights into emerging design trends and the impact on the India’s growing role in the global high tech community.

KEYNOTE Several factors are causing the ASIC market and design landscape to change rapidly. Where deeper submicron CMOS process technologies continue to provide power, performance and area advantages for digital circuitry, technologies like analog, embedded flash, embedded DRAM and RF do not scale as well. In addition to this, the integration of more and more CPUs into the SoC is putting more and more strain on the interfaces to main memory becoming the performance bottleneck.

Though factors like these are slowing down the continued integration of additional circuitry onto a single die, the advent of new through-silicon-via (TSV) based 2.5D and 3D packaging technologies are enabling the integration of more die into a single package. Compared to chip-to-chip interfaces in the system, interposer-based die-to-die interfaces provide the potential for increased bandwidth at reduced power levels. Standardization initiatives like JEDEC's WideIO interface are looking to exploit the advantages brought by 2.5D and 3D packaging techniques.

In this presentation we will take a deeper look at the promise the new 2.5D and 3D technologies bring for the ASIC development community. As Xilinx deploys a 2.5D stack in its latest high-end FPGA, and Micron is prototyping its 3D Hybrid Memory Cube (HMC) memory, it's widely believed ASICs will be next.

TECHNICAL SESSION IC designs at 20nm will have new structures and new techniques that impact parasitic extraction. Designers will need new models for both local interconnect and device-level structures. They will also need efficient ways to handle colored vs. non-colored data for double patterning, and more extensive corner management. 3D-IC could also require a paradigm shift in how we represent traditional parasitics and new TSV models. This session will cover how the Calibre product line can address these critical challenges.

TECHNICAL SESSION Advanced fill is the next big challenge at leading edge nodes. Traditional dummy fill can no longer meet all the subtle requirements of advanced nodes, which go far beyond maintaining planarity during the CMP process. Mentor’s Calibre SmartFill solution is ready today to address advanced fill dependencies at 20nm such as Rapid Thermal Annealing (RTA), etch rates, stress and other factors. An intelligent fill solution meets the new requirements while delivering smaller post-fill GDS database size and faster runtimes without manual customization or modification. Come and learn about what is driving the new fill approaches and how Calibre SmartFill can meet the new requirements in your design flows.

TECHNICAL SESSION The adoption of Formal Verification technology has traditionally been encumbered by performance, capacity and ease of use issues.With the Questa Static solution complete SoC designs, greater than 150M gates in size, can now be analyzed in a single step. Tens of thousands of assertions for multi-million gate design blocks can now be proven in a matter of hours. Huge strides have been made in advancing the usability of the formal tools, with the development of new features and refinement of methodologies, so that this groundbreaking power has been brought to a whole new level of automation.In this session, we discuss five solutions offered with the Questa Static products that you can incrementally add to your design flow and that are must-have components in any complete verification flow:• Clock domain crossing (CDC) verification to eliminate the risk of metastability issues in silicon• Automatic formal checks for push-button checking to find functional issues without writing a testbench or assertions• Formal code coverage closure to prune unreachable bins from the coverage model• Static X-propagation verification to verify that X-optimism is not masking design bugs• Connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections

TECHNICAL SESSION Not only are speeds of systems increasing rapidly and now in the multiple Gbps, but the percentage of high speed nets common at over 75%. This all requires extensive analysis and verfication during the design process versus producing physical prototypes and testing them in the lab. This session will discuss these required analysis tools in detail for signal integrityanalysis of DDRx and SERDES interconnects, Power Distribution Network analysis,the inclusion of 3D SI analyis for via structures, and Analog simulation.

TECHNICAL SESSION In complex analog design and at advanced nodes, ICs are more sensitive to electrical overstress (EOS) failures and require additional checks that cannot be performed using standard solutions such as design rule (DRC), layout vs. schematic (LVS) or electrical rule checking (ERC). IC designers need new techniques to validate that all required protection structures are in place, and that the complex and special design rules are met. In this session TowerJazz will describe its Power Management technology and associated complex design rules, as well as its ESD objectives and challenges. The session will also describe how TowerJazz is using Calibre PERC to increase the quality of design and improve long-term reliability. A case study will describe the techniques used, how checks were developed in Calibre PERC, and the results achieved.

TECHNICAL SESSION Delivering a correct, high yielding product on time becomes more and more difficult at each manufacturing node due to an increase in number and complexity of design-sensitive issues. This session describes how diagnosis-driven yield analysis (DDYA) accelerates time to root cause of yield loss and identifies yield limiters using statistical analysis of volume test diagnosis data in a way that augments traditional solutions. First, scan diagnosis determines the defect classifications and locations for each failing die, based on the design description, scan test patterns, and tester fail data. Second, specialized statistical analysis is used to identify and separate systematic yield limiters in seemingly random fail data and select the most suitable devices for failure analysis. The presentation will cover recent advances in diagnosis technology and diagnosis results analysis such as layout-aware diagnosis and DFM-aware yield analysis, as well as results from several industrial case studies.

TECHNICAL SESSION As many design teams can attest, fast emulation has become a critically important verification component for large and complex systems-on-chip (SoCs). Today, emulation is used to test the hardware aspects of a SoC design and to verify the integration of hardware and the embedded software. Attend this session to hear how the Veloce platform provides high-speed emulation solutions for the verification of SoCs in a “virtual lab” environment. Each application is software-based, creating a non-intrusive environment that is reproducible, expandable, and available to share between multiple verification teams.

TECHNICAL SESSION PCB complexity is increasing at almost an exponential rate. To leverage this complexity int more competitive products while meeting productivity and time to market goals requires advanced design technologies as provided only by Mentor Graphics. This session will illustrate some of those technologies such as BGA breakouts, advanced routing, and powere distribution network creation.

TECHNICAL SESSION 20nm and 3D-IC bring significant changes to how designers must perform physical verification (e.g. DRC, LVS, PEX, Fill, etc.). Come learn about the challenges and how to prepare so that you can quickly ramp your next design to production. This is a one-time only, limited seating event for advanced Calibre users. Register today to reserve your spot.

TECHNICAL SESSION The growing adoption of 3D packages is driving the need for advanced test solutions. The good news is that many of the advanced Tessent® solutions developed for leading edge 2D designs are well suited for addressing new 3D test requirements as well. A critical requirement for ensuring acceptable 3D package yields is very high quality of the bare die going into the package. A proven approach to achieving this low defect per million (DPM) goal is the use of ATPG patterns generated using the Tessent cell-aware fault model based capability. The rapid adoption of memory stacked on logic applications requires new methodologies for testing the bare memories and their TSV connections to the base logic die. The Tessent MemoryBIST capabilities developed for addressing bussed internal ARM core memories as well as unique features for testing external DRAM memories are perfectly suited for testing stacked bare DRAM die. These capabilities and many other advanced features of the Tessent family of test products will be discussed in this session.

TECHNICAL SESSION The era of platform-based SoCs has arrived. By increasing the granularity of pre-integrated and reused IP within an SoC platform, subsystems allow faster design and delivery of platform-based systems. Reusable subsystems represent the next advancement towards ever larger, reusable design functions. However, with each step in the size of reusable blocks, the integration and system verification complexities expand exponentially, from limited parameterization to partial and full programmability.

To realize the benefits of platform-based SoCs, users must be able to develop, optimize, integrate and verify differentiating hardware blocks and the software that defines the final system. Time-to-market and quality are keys to success. Software development and validation must begin on day one to avoid costly schedule delays. Multi-core platforms, with extensible coherent memory, increase the SoC architectural design, integration, verification, and debug challenges. Full system verification and test must begin early in order to adequately test the full breadth and depth of system architecture and performance and deliver the quality that today’s market demands.

In this session, we will cover the process of defining an ARM-based design based on platform subsystem IP, the development and integration of hardware acceleration blocks, analyzing system performance criteria, verification of the SoC functionality, the development and validation of software using virtual prototyping and acceleration technology and verification from block to SoC to full system.

TECHNICAL SESSION Poor reliability of a product can lead to extensive waranty cost, product recalls and bad repuitation. There are many causes of poor reliability such as excessive heat, vibration ans shock, marginal manufacturing, and poor power distribution network design. This session will discuss how virtual prototyping analysis can predict long term reliability issues and help designers eliminate them without the use of expensive and time consuming physical prototyes and test chamber testing.

TECHNICAL SESSION Beginning at 20nm, the challenges of lithographic imaging require the use of double patterning techniques, which bring new requirements into the design and verification space. In this session we will take a deep dive into the requirements and discuss the methodologies and tool solutions you need to be successful at 20nm.

TECHNICAL SESSION With the advent of 20nm, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time they also face a slew of new design challenges at 20nm that severely impact design performance, power and time to market. Challenges such as double patterning aware placement and routing, DFM, extraction and timing, larger design sizes, stringent low power requirements and process variations have a major impact on design performance and productivity. This session will highlight some of the key capabilities and differentiators that Olympus-SoC offers to address complex 20nm challenges, and also provides a sneak peak of the product roadmap.

TECHNICAL SESSION With the explosion of consumer electronics, designing for low power has become an important design constraint and a key differentiating factor. In this session, Calypto will cover its two platforms for optimizing power across the entire SoC: 1) PowerPro Platform: Targeted at RTL designers who want to reduce power for legacy IP and existing RTL designs. The Power Platform is based on patented sequential analysis technology which allows PowerPro to looks across 100’s of clock and functional boundaries to find greater power savings. 2) Catapult LP (Low-Power) is targeted at hardware designers who want to use SystemC or C++ to optimize power at the architecture level using high level synthesis. Catapult LP is Calypto’s newest product announced May 29th, 2012 at the Design Automation Conference (DAC). Catapult LP takes advantage of Calypto’s unique PowerPro® technology by embedding it “under the hood” to optimize designs at the architecture level where 80% of power decisions are made. Come hear how Calypto’s proven technology can help you meet your low power goals.

TECHNICAL SESSION The design of today's products requires the collaboration of muliple design team members and multiple development disciplines such as MCAD, ECAD (engineers and layout designers), FPGA, RF desingers and manufacturing. This session will discuss how mentor's unique systems design technologies enable these team members to collaborate real time and reduce their schedules, increase quality and improve productivity. Discussions will include design-for-manufacturability and manufacturing interfacing, concurrent design definition and layout, FPGA/IC package/PCB co-design, and RF/Digital/Analog collaboration.