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ARM
Main
  • The Promise of 2.5D & 3D ASIC Design Abstract

    KEYNOTE Several factors are causing the ASIC market and design landscape to change rapidly. Where deeper submicron CMOS process technologies continue to provide power, performance and area advantages for digital circuitry, technologies like analog, embedded flash, embedded DRAM and RF do not scale as well. In addition to this, the integration of more and more CPUs into the SoC is putting more and more strain on the interfaces to main memory becoming the performance bottleneck.

    Though factors like these are slowing down the continued integration of additional circuitry onto a single die, the advent of new through-silicon-via (TSV) based 2.5D and 3D packaging technologies are enabling the integration of more die into a single package. Compared to chip-to-chip interfaces in the system, interposer-based die-to-die interfaces provide the potential for increased bandwidth at reduced power levels. Standardization initiatives like JEDEC's WideIO interface are looking to exploit the advantages brought by 2.5D and 3D packaging techniques.

    In this presentation we will take a deeper look at the promise the new 2.5D and 3D technologies bring for the ASIC development community. As Xilinx deploys a 2.5D stack in its latest high-end FPGA, and Micron is prototyping its 3D Hybrid Memory Cube (HMC) memory, it's widely believed ASICs will be next.

Presenter: Hans Bouwmeester, Sr. Director of IP, ARM Center-of-Excellence, Open-Silicon

Calypto
Room 3
  • Calypto Low Power RTL and ESL Solution Abstract

    TECHNICAL SESSION With the explosion of consumer electronics, designing for low power has become an important design constraint and a key differentiating factor. In this session, Calypto will cover its two platforms for optimizing power across the entire SoC: 1) PowerPro Platform: Targeted at RTL designers who want to reduce power for legacy IP and existing RTL designs. The Power Platform is based on patented sequential analysis technology which allows PowerPro to looks across 100’s of clock and functional boundaries to find greater power savings. 2) Catapult LP (Low-Power) is targeted at hardware designers who want to use SystemC or C++ to optimize power at the architecture level using high level synthesis. Catapult LP is Calypto’s newest product announced May 29th, 2012 at the Design Automation Conference (DAC). Catapult LP takes advantage of Calypto’s unique PowerPro® technology by embedding it “under the hood” to optimize designs at the architecture level where 80% of power decisions are made. Come hear how Calypto’s proven technology can help you meet your low power goals.

Blue Pearl

Event Sponsors

ARM

ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM at http://www.arm.com.

Calypto

Calypto® Design Systems, Inc. empowers designers to create high quality, low power ASIC and FPGA hardware products. By delivering best-in-class tools for power optimization, functional verification and ESL synthesis, Calypto provides the most comprehensive ASIC and FPGA implementation flows in the market. Calypto's three product families (PowerPro®, Catapult® and SLEC®) offer customers solutions ranging from RTL power reduction to C++/SystemC high-level synthesis. More information about Calypto is available at http://www.calypto.com.

Blue Pearl

Blue Pearl Software focuses on solving RTL analysis challenges. Blue Pearl Software Suite offers automatically generated Synopsys Design Constraints (SDCs), offers lint and clock domain crossing (CDC) checking and a Visual Verification Environment. These capabilities reduce the number of iterations required to close timing of multi-language (VHDL, SystemVerilog) designs. The software runs natively on Windows and Linux, and is used for FPGA, ASIC and SOC designs. More information about Blue Pearl is available at http://www.bluepearlsoftware.com.