Sign In
Forgot Password?
Sign In | | Create Account

Mentor Forum Israel

Mentor Forum Israel Logo

Join the Mentor Forum Israel 2015 and learn how our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip design.

Choose from numerous presentations, including keynotes and breakout tracks on topics addressing Functional Verification and Emulation; Physical Verification and Design for Test; PCB Design & Analysis and IC Design & Test.

Don’t miss this one day conference which brings together technology users, developers, and industry experts to network and share best practices.

Hilton Tel Aviv


March 24th 2015


Hilton Tel Aviv
Independence Park
Tel Aviv, Israel
Tel: 972-3-971-5000

Register now

Featured Session

Secure Silicon: Enabler for the Internet of Things

Dr. Wally Rhines

Keynote Wally Rhines, Chairman & CEO, Mentor Graphics

As electronic system hackers penetrate deeper—from applications to embedded software to OS to silicon—the impact of security threats is growing exponentially. Viruses and malware in the operating system, or application layer, are major concerns, but only affect a portion of users. In contrast, even small malicious modifications or compromised performance in the underlying silicon can devastate system security for all users. Growth of the Internet of Things magnifies the impact of the security problem by orders of magnitude.

Since hardware is the root of trust in an electronic product, EDA companies will be increasingly pressured to solve the silicon security problems for their customers. This requires a new paradigm in silicon design creation and verification. The traditional EDA role is to design and then verify that the silicon does what it is supposed to do. Creating secure silicon, however, requires that verification ensure that the chip does nothing that it is NOT supposed to do.

The industry is at the first stage of Secure Silicon awareness; it’s going to become big business as future events unfold. Join Wally Rhines as he examines the growing threats to silicon security and EDA’s possible solutions.

The Next Big Thing in Test Compression!

Keynote Thomas Rinderknecht, Mentor Graphics

Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This session will begin with a review of leading-edge test compression features and techniques and will then introduce and focus on an exciting new technology, called EDT Test Points, that has been developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. Numerous customer beta engagements have shown that EDT Test Points can reduce compressed pattern counts on an average by a multiplicative factor of 2-4X, without affecting test coverage, and even for designs with the most aggressive embedded compression configurations.

Achieving Design Effectiveness

Keynote A.J. Incorvaia, Vice President and General Manager, Board Systems Division, Mentor Graphics

A design process optimized for speed often just means more ECOs; true effectiveness is achieved with speed AND quality. Quality is achieved by adhering to constraints throughout the design process to produce correct-by-construction designs. Quality also means incorporating a virtual prototyping process that optimizes manufacturability and performance of the end-product. This session will identify critical quality challenges, and an effective design process to address them.

DFT Technology Seminar – IJTAG Technology – IEEE 1687 | Enabling the ecosystem from chip to system

Technical Session Presented by ASSET InterTech and Mentor Graphics

The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you than legacy probe-based technologies. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips. Don’t miss the chance to learn how to tap into this useful IP. You will have the opportunity to learn from experts from both Mentor Graphics and ASSET InterTech.

Technical Focus Breakout Tracks

Mentor Graphics will be discussing the latest innovations in these key focus areas:

Don’t miss your opportunity to:

  • Meet face-to-face with experts from Mentor Graphics to discuss the latest trends in EDA.
  • Take in highly valuable content from technical presenters in more than 25 sessions
  • See customer presented case-studies
  • Meet our exhibiting partners and discover how they can help your company
  • Network with 500+ peers in a nice environment – be part of the Mentor community!
  • Have the chance to win the Lenovo Yoga Tablet 2

No Conference Fee
Attendance at this annual event is free (Lunch is included), but you do need to register in advance.

Register to Win

Register for Mentor Forum Israel and be entered to win the Lenovo Yoga Tablet 2!


Join interesting case studies and find out how other customers use Mentor Graphics solutions in real life:

DFT track, 12:05 PM - 12:55 PM

TestKompress Test Point Insertion
Presenter: Assaf Gindi, DFT Engineer, Marvell Semiconductor

DFT track, 2:25 PM - 3:10 PM

Hierarchical ATPG implementation - Using recursion & hierarchical clock control
Presenter Dan Trock, DFT Leader, Annapurna Labs

DFT track, 2:25 PM - 3:10 PM

Application of Tessent Yield Insight at Marvell, a case study
Presenter Michael Degtyar, NP Test and Product Engineering manager, Marvell Semiconductor

Functional Verification and Emulation track, 11:20 AM - 12:05 PM

Productive Software - Hardware debug techniques for pre-silicon SoC level emulation platforms.
Presenter: Lior Cohen, Broadcom

Functional Verification and Emulation track, 11:20 AM - 12:05 PM

Experience with Large scale SoC Verification Acceleration
Presenter: tbd

PCB System Design track, 12:05 PM - 12:55 PM

Exhaustive SI and PI analysis on technology leadership award winning design
Presenter: Itzhak Hirshtsl, Team Leader Signal Integrity, IAI Elta

Physical Verification track, 10:35 AM - 11:20 AM

Adopting CalibreView format for XRC in Analog Design environment

Physical Verification track, 12:05 AM - 12:55 AM

Calibre DRV, Calibre Autowaivers and HTML reports

Online Chat