The Big Squeeze
Keynote Wally Rhines, Chairman & CEO, Mentor Graphics
For decades, we’ve known it was coming and now it’s here. Moore’s Law—which is really just a special case of the “learning curve”—can no longer drive the 30% per year reduction in cost per transistor, beginning with the 20/16/14 nm generation. Either we find innovations beyond just shrinking feature sizes and increasing wafer diameter or we slow our progress down the learning curve, introducing innovative new electronic capabilities at a slower rate than in the past.
There are lots of alternatives, including a reduction in profitability of the members of the supply chain, to keep the progress continuing at the same rate as the last fifty years. Dr. Rhines will review the mathematical basis for the dilemma and, with his brand of humor, provide a roadmap of possibilities for the decade ahead.
Introducing a Major Advance in PCB Systems Design: Xpedition VX
Keynote Henry Potts, Vice President and General Manager, Systems Design Division, Mentor Graphics
The evolution of Xpedition began in 2005 with the first release of an integrated flow for schematic and layout. In 2007 we met the demands of enterprise IT environments by facilitating client/server architectures. Expedition Enterprise 7.9.x in 2009 expanded mainstream deployment with a highly stable environment.
Over the months to come, with the Xpedition VX launch, we will continue to deliver solutions that are unmatched in our industry. This is the foundation for the next generation of proven, innovative thinking as we continue to address our enterprise customers’ needs. This presentation will address the industry challenges that VX addresses, as well as key release highlights.
Veloce - The Cornerstone of SoC Verification
Emulation is no longer a luxury - it is fundamentally an essential part of the SoC verification process. The success of Veloce and its role in increasing the wider adoption of emulation has brought this technology to the forefront of verification methodologies across a range of applications, and is used by leading electronics companies worldwide. In this session we examine how Veloce’s innovations have created solutions and capabilities that deliver the best-in-class emulation technologies.
Join interesting case studies and find out how other customers use Mentor Graphics solutions in real life:
- Choosing scan hierarchical flow solution - Dilemmas and considerations
Presenter: Shlomi Sde-Paz, DFT Manager, Freescale Semiconductor
DFT/P&R track, 11:10 AM - 11:55 AM
- Isolating Blocks during Scan Testing in a High-Quality Large Industrial Design IP through Wrapper Insertion
Presenter: Shahar Ben-Aharon, DFT Manager, AMD Israel
DFT/P&R track, 2:30 PM - 3:15 PM
- Using the power of Tessent Shell for quick ATPG ramp up
Presenter: Kostya Korchiomkin, DFT Engineer, Freescale Semiconductor
DFT/P&R track, 2:30 PM - 3:15 PM
Technical Focus Breakout Tracks
Mentor Graphics will be discussing the latest innovations in these key focus areas:
Don’t miss your opportunity to:
- Listen to tailor made technical sessions and executive presentations that will give you the latest news on EDA technologies and offer you a preview of what's coming.
- See customer presented case-studies.
- Meet our exhibiting partners and discover how they can help your company.
- Take advantage of great networking opportunities.
No Conference Fee
Attendance at this annual event is free (Lunch is included), but you do need to register in advance.
Register to Win
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