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Mentor Forum: DFT, Place & Route

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Technical Session
  • Advanced Hierarchical DFT Topics
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    TECHNICAL SESSION SoC designs can implement many variations of a hierarchical DFT architecture and pattern generation techniques including:
    cores embedded in cores, combining wrapped and unwrapped cores and merging top level patterns with core level patterns.
    This presentation will provide an overview of tool capabilities that address these scenarios as well as review how iJTAG can provide greater automation for hierarchical ATPG.

    This presentation includes a case-study

    Choosing scan hierarchical flow solution - Dilemmas and considerations

    The industry trend for emerging size Soc's puts a real challenge on preparing Scan test suite, in many aspects like: ATPG run time, computing resources and test time.
    This presentation will lead us through a testcase from Freescale to realize the difficulty faced on scan suite preparation for a new Soc.
    It will then show how using the scan hierarchical flow (Retargeting) is helping to overcome the obstacles. Preliminary results will be shared.

    Shlomi Sde-Paz, DFT Manager, Freescale Semiconductor

  • Automotive ATPG: Towards zero DPM and in-system testing
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    TECHNICAL SESSION The growing number of chips in cars and the increasing complexity of these chips has focussed interest in looking for effective DFT methodologies. Due to safety critical requirements coming from automotive standards like ISO 26262, two test goals emerge from them.
    They are a zero DPM requirement and an in-system capability. This talk will discuss the test methodology and test solutions that leading automotive chip providers are implementing today.

  • DFM-Aware ATPG: A physical layout test methodology
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    TECHNICAL SESSION Silicon defects can occur during the manufacturing process due to certain physical layout structures. Standard ATPG methods are not physically aware and are based on assumptions which are checked using DRC. Further, standard ATPG will optimise the test patterns to reduce tester volume. Thus, standard ATPG cannot always detect some physical defects which are highly prone due to particular layout structures. This talk will describe a methodology which was successfully implemented on customer production designs to significantly improve physical defects.

  • Improve Logic Test with a Hybrid ATPG/BIST Solution
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    TECHNICAL SESSION Two test strategies are used to test virtually all IC logic - ATPG with test pattern compression, and logic BIST.
    ATPG has been dominant for years, and is now used for full-chip test across the electronics industry. The growth in ICs for safety critical applications, like automotive and medical, has boosted the demand for BIST. The presentation will deal with a mixture of both – hybrid solution for logic test.

    This presentation includes case-studies

    Case study 1
    Isolating Blocks during Scan Testing in a High-Quality Large Industrial Design IP through Wrapper Insertion

    As the industry has been moving toward large scale SOC designs, the “divide and conquer” strategy gets fundamental for fast scan test suite development and the resulting silicon bring-up.
    This presentation will lead us through the discussion of one of the building blocks of this strategy – isolation of SOC design’s blocks/hard macros. It will then show different wrappers’ insertion options, rules and cost of the implemented solution using the shared wrapper flow.

    Shahar Ben-Aharon, DFT Manager, AMD Israel

    Case study 2
    Using the power of Tessent Shell for quick ATPG rampup

    Supporting ATPG environment for physical blocks and keeping it updated during design development takes significant time and leads to high overhead on DFT team.
    This presentation describes new method for automatic extraction of ATPG input parameters directly from the netlist.
    This method requires minimal knowledge of input netlist. It is based on Tessent Shell tcl interface and widely uses latest tool commands accessing design objects, collections and netlist attributes.

    Kostya Korchiomkin, DFT Engineer, Freescale Semiconductor

  • Olympus-SoC: Achieving Best Power Performance & Area at Advanced Nodes
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    TECHNICAL SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (28nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC/DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

Products: Olympus-SoC
  • Test Efficiency is crucial for Time-To-Market while maintaining low DPM
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    TECHNICAL SESSION The DFT engineer is always striving for test efficiency as a key goal but it is continually evolving. The economic pressures are Time to Market (TTM) and reducing or, at least, maintaining a current level of DPM. When technology nodes are changed or there is a new design start which has increasing complexity, performance and low power needs then the established DFT methodologies are challenged.
    Now, each time a new DFT capability or technology is introduced, the DFT engineer gets an opportunity to adapt and improve their test efficiency methodologies. This talk will touch on what today’s leading-edge DFT engineers are implementing and adapting in their test efficiency methodologies.