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Mentor Forum: DFT
(Tessent® Product Suite )

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Featured DFT (Tessent Product Suite ) Events

Keynote: The Next Big Thing in Test Compression! Tuesday, March 24, 10:35 AM

Technical Session Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This session will begin with a review of leading-edge test compression features and techniques and will then introduce and focus on an exciting new technology, called EDT Test Points, that has been developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. Numerous customer beta engagements have shown that EDT Test Points can reduce compressed pattern counts on an average by a multiplicative factor of 2-4X, without affecting test coverage, and even for designs with the most aggressive embedded compression configurations.

DFT Technology Seminar – IJTAG Technology – IEEE 1687 | Enabling the ecosystem from chip to system presented by ASSET InterTech and Mentor Graphics Tuesday, March 24, 11:20 AM

Technical Session The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you than legacy probe-based technologies. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips. Don’t miss the chance to learn how to tap into this useful IP. You will have the opportunity to learn from experts from both Mentor Graphics and ASSET InterTech.

F = Full registration required

Technical Session
  • ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 2
    Toggle Abstract

    TECHNICAL SESSION ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 2

    Case study: TestKompress Test Point Insertion
    Presenter: Assaf Gindi, DFT Engineer, Marvell Semiconductor
    Abstract: In modern scan-based testing of semiconductor devices the patterns count is increasing dramatically. ATE test cost also increases as the pattern count increases. This case study describes the results of a successful TestKompress test point insertion evaluation at Marvell Semiconductor. The technology offers automatic insertion of limited control and observe points which reduced pattern count and ATE test cost whilst maintaining coverage.

  • ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 3
    Toggle Abstract

    TECHNICAL SESSION ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 3

  • Customer Case studies presented by Annapurna Labs and Marvell Semiconductor
    Toggle Abstract

    TECHNICAL SESSION Case study:
    Hierarchical ATPG implementation using recursion & hierarchical clock control
    Presenter: Dan Trock, DFT Leader, Annapurna Labs
    Abstract: As the hierarchical ATPG flows become a necessity due to the design size and complexity there is a growing need for less timing- and area- consuming core isolation techniques. Clock control schemes are also required which support a hierarchical test structure as more logic is left outside the wrappers.
    This paper presents a practical implementation of a multi-level hierarchical test flow utilizing a hierarchical clock control design combined with shared style wrapping technique offered by today’s EDA tools.

    Case study:
    Application of Tessent Yield Insight at Marvell, a case study
    Presenter: Michael Degtyar, NP Test and Product Engineering manager, Marvell Semiconductor
    Abstract: Case study – applying Tessent Yield Insight to localize systematic silicon defects and eliminate elevated DC SCAN yield loss.

  • DFT Technology Seminar – IJTAG Technology – IEEE 1687 | Enabling the ecosystem from chip to system presented by ASSET InterTech and Mentor Graphics
    Toggle Abstract

    TECHNICAL SESSION The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you than legacy probe-based technologies. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips. Don’t miss the chance to learn how to tap into this useful IP. You will have the opportunity to learn from experts from both Mentor Graphics and ASSET InterTech.

  • Keynote: The Next Big Thing in Test Compression!
    Toggle Abstract

    TECHNICAL SESSION Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This session will begin with a review of leading-edge test compression features and techniques and will then introduce and focus on an exciting new technology, called EDT Test Points, that has been developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. Numerous customer beta engagements have shown that EDT Test Points can reduce compressed pattern counts on an average by a multiplicative factor of 2-4X, without affecting test coverage, and even for designs with the most aggressive embedded compression configurations.

Presenter: ThomasRinderknecht, Staff Engineer, D2S DFT R&D Development, Mentor Graphics