TECHNICAL SESSION Two test strategies are used to test virtually all IC logic - ATPG with test pattern compression, and logic BIST.
ATPG has been dominant for years, and is now used for full-chip test across the electronics industry. The growth in ICs for safety critical applications, like automotive and medical, has boosted the demand for BIST. The presentation will deal with a mixture of both – hybrid solution for logic test.
This presentation includes case-studies
Case study 1
Isolating Blocks during Scan Testing in a High-Quality Large Industrial Design IP through Wrapper Insertion
As the industry has been moving toward large scale SOC designs, the “divide and conquer” strategy gets fundamental for fast scan test suite development and the resulting silicon bring-up.
This presentation will lead us through the discussion of one of the building blocks of this strategy – isolation of SOC design’s blocks/hard macros. It will then show different wrappers’ insertion options, rules and cost of the implemented solution using the shared wrapper flow.
Shahar Ben-Aharon, DFT Manager, AMD Israel
Case study 2
Using the power of Tessent Shell for quick ATPG rampup
Supporting ATPG environment for physical blocks and keeping it updated during design development takes significant time and leads to high overhead on DFT team.
This presentation describes new method for automatic extraction of ATPG input parameters directly from the netlist.
This method requires minimal knowledge of input netlist. It is based on Tessent Shell tcl interface and widely uses latest tool commands accessing design objects, collections and netlist attributes.
Kostya Korchiomkin, DFT Engineer, Freescale Semiconductor