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Mentor Forum: Functional Verification

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Technical Session
  • Optimizing for Power Efficient Design
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    TECHNICAL SESSION With the explosion of portable electronic devices, designing for low-power is a critical design constraint. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, via automated tools or manually. This session will review how Power Analysis can be done at the RTL level to drive low power optimizations.

  • Providing Coverage
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    TECHNICAL SESSION The first FPGA Verification session “Providing Coverage” describes code and functional coverage, and how each of these verification techniques can be applied to your verification process. Step by step adoption flows are presented. Answer questions about how coverage can improve FPGA lab productivity. What is the benefit of adding functional coverage? What is the impact of code coverage? How to deploy new processes and manage FPGA project demands. Why does coverage matter and how to leverage FPGA verification process improvements.

  • Technology Evolution in Functional Verification: Trends, Challenges and Solutions
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    TECHNICAL SESSION Every two years, the Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. Results of the just-completed survey demonstrate an ongoing convergence of SoC design practices toward a common methodology, independent of the specific tools being used. This type of methodology standardization normally drives the EDA industry into a productive wave of innovation, as EDA companies develop a variety of new tools to optimize results achieved with a standard methodology.
    This session identifies the common attributes of SoC methodology that are emerging, highlights specific capability enablers for the further optimization of SoC design verification, and illustrates how Mentor Graphics’ combines advanced simulation, formal verification, and emulation technology to help you exceed your verification goals

  • Using standard database techniques for advanced SoC analysis on multiple platforms
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    TECHNICAL SESSION SoC verification has long been considered as a simple extension of block level verification, but is gradually emerging as a distinct domain requiring its own tools and methodologies. Different verification objectives make reuse of coverage models and reference models of very little use, while the difference in size turn platform independence into a crucial requirement. Taking the example of SoC performance verification we will look into the various data sources that are available from SoCs on multiple platforms and at how standard database techniques can operate on those to provide meaningful analysis and visualization.

  • UVM: Out of Committee into Productivity
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    TECHNICAL SESSION This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.

  • Verification:  Automate When Possible
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    TECHNICAL SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!