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Mentor Forum: Functional Verification + Emulation (Questa® Verification Platform; Veloce® Emulation Platform)

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Technical Session
  • Customer case studies
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    TECHNICAL SESSION Case study: Productive Software - Hardware debug techniques for pre-silicon SoC level emulation platforms.
    Presenter: Lior Cohen, Broadcom
    Abstract: Policymakers worldwide have set aggressive targets for broadband coverage, challenging governments and service providers alike to connect the world's citizens to the Internet. Fiber solutions (such as GPON\EPON) help meet that challenge, allowing service providers to deliver faster internet access.
    Fiber solutions designs require high speed rates delivered in low-cost implementations for high-volume markets. As a result, the design of Network systems introduces challenges for both design and Software teams. We present the usage of emulation as a key tool in achieving the Fiber design and Software teams targets. Co-verification of HW and SW is usually a joint effort of DV and SW development teams.
    Enabling efficient SW debugging capabilities in pre silicon phase is a key factor for the success of this effort.
    The presentation will describe the usage of CODELINK and Veloce emulator for building a highly productive pre-silicon SoC debug platform.
    Such platform allows debug of real SW code involving both an embedded processor and an external PCIe host.

    Case study: Experience with Large scale SoC Verification Acceleration
    Abstract: User experience of advanced Veloce tools for Verification acceleration.

  • Delivering SoC Verification in a World of the Internet-of-Things
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    TECHNICAL SESSION IoT interconnect-ness means more verification complexity, more software, low power verification, and time to market pains. We’ll describe how Veloce based verification solution will address the verification of growing design complexities related to the IoT.

  • Get Your FPGA Design out of the Lab Faster
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    TECHNICAL SESSION Spending too much time in the lab debugging your FPGA? FPGAs have grown large and complex; so has the task of validating the functionality after it has passed all the tests for area, performance and power. If there is a problem with your FPGA during system integration testing, where do you start looking for issues? This presentation introduces new validation methods to help you instrument your FPGA design so that problems are easier to find as they happen.

  • Making Simulation and DSP algorithm talk
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    TECHNICAL SESSION DSP Algorithm development flow requires that the algorithm, often modeled in Matlab, is later implemented in RTL, and that this implementation is verified against the Matlab model. During the RTL implementation and verification phase, Matlab can be used in a variety of roles: as stimuli generator, as a checker, as a model for non-existing parts, or for analysis. All of these roles require, however, that some channel of communication is established between the RTL simulator and Matlab. In this session we will learn about the existing options to pass data to and from Matlab, and discuss their respective merits and shortcomings. We will then present a new solution that is designed to solve some of the shortcomings in existing solutions, and talk about future directions and roadmap for further integration.

  • Technology Innovation in Functional Verification - Challenges and Solutions
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    TECHNICAL SESSION This session identifies the emerging common attributes of verification methodology, highlights specific capability enablers for the further optimization of ASIC and FPGA designs verification. The session illustrates how Mentor Graphics’ combines advanced simulation, verification management and SW approach technology to help users exceed their verification goals in time.