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Mentor Forum: Physical Verification

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Technical Session
  • Calibre AutoWaivers Flow
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    TECHNICAL SESSION When verifying a design, certain rule check violations can be waived by the foundry. Such waivers need to be managed in the results output so that they can be preserved for analysis and validation. Inspecting such waivers manually consumes much time. IP vendors can provide IP with waiver information and allow the fabless designer to address only real SOC errors for debugging. The session will show you how Calibre addresses this issue.

  • Calibre for Legacy processes
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    TECHNICAL SESSION Communciation around new features and advacend nodes always drive the crowd to the smaller ndoes available. This unfortunately hide the large variety of legacy nodes which are in production today and which also requires advanced techniques to ease the lfie of the designers or the fab engineer. We will concentrate on those so called legacy nodes which by the way are feeding our ecosystem. We will span the large variety of Calibre tools, batch and interactive which allows end users to eprform DRC/LVS checks, debug complicated issues, bring Calibre int eh design environment.

Products: Calibre nmDRC Calibre nmLVS Calibre OPCpro Calibre PERC Calibre Interactive Calibre RVE Calibre DesignRev
  • Comprehensive Circuit Reliability with Calibre PERC
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    TECHNICAL SESSION Implementing a robust IC verification methodology that addresses circuit reliability is increasingly difficulty for all process nodes. Larger nodes are seeing new challenges that were not apparent in previous generations, such as increasing design complexity. Smaller nodes are seeing greater sensitivity to electrical overstress (EOS), current density and electro-migration issues. For designs with multiple complex power domains, transistor-level power intent verification can be difficult to verify, but new tools are emerging to automate such checking by leveraging UPF. This session describes how Calibre PERC can provide a comprehensive reliability verification platform to address these problems.

Products: Calibre PERC Calibre LVS
  • DFM at Advanced Nodes
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    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Products: Calibre LFD Calibre YE/YA/YS
  • New design challenges at 28nm and how Calibre addresses them
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    TECHNICAL SESSION Many of you have recently moved from older process technologies to the project that is based on 28nm process. 28nm brings many new hurdles to the physical verification and the parasitic extraction that Calibre can solve. Please join this session and become ready for design work at 28nm!

  • Physical Verification with Multi-Patterning for Advanced Nodes
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    TECHNICAL SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

Products: Calibre DRC Calibre nmDP