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Tuesday, March 24

Tuesday, March 24

8:00 AM - 9:00 AM  1 session

  • REGISTRATION
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    LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

ALL DELEGATES

9:00 AM - 9:10 AM  1 session

  • WELCOME
ALL DELEGATES

9:10 AM - 10:10 AM  1 session

  • Keynote : SECURE SILICON: ENABLER FOR THE INTERNET OF THINGS
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    KEYNOTE As electronic system hackers penetrate deeper—from applications to embedded software to OS to silicon—the impact of security threats is growing exponentially. Viruses and malware in the operating system, or application layer, are major concerns, but only affect a portion of users. In contrast, even small malicious modifications or compromised performance in the underlying silicon can devastate system security for all users. Growth of the Internet of Things magnifies the impact of the security problem by orders of magnitude.

    Since hardware is the root of trust in an electronic product, EDA companies will be increasingly pressured to solve the silicon security problems for their customers. This requires a new paradigm in silicon design creation and verification. The traditional EDA role is to design and then verify that the silicon does what it is supposed to do. Creating secure silicon, however, requires that verification ensure that the chip does nothing that it is NOT supposed to do.

    The industry is at the first stage of Secure Silicon awareness; it’s going to become big business as future events unfold. Join Wally Rhines as he examines the growing threats to silicon security and EDA’s possible solutions.

Presenter: Dr Walden Rhines, CEO & Chairman of the Board, Mentor Graphics
ALL DELEGATES

10:10 AM - 10:35 AM  1 session

  • MORNING BREAK
ALL DELEGATES

10:35 AM - 11:20 AM  5 sessions

  • Calibre platform for advanced physical verification
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    TECHNICAL SESSION Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster. Case study: Adopting CalibreView format for XRC in Analog Design environment

Physical Verification (Calibre Platform)
  • Keynote: The Next Big Thing in Test Compression!
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    TECHNICAL SESSION Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This session will begin with a review of leading-edge test compression features and techniques and will then introduce and focus on an exciting new technology, called EDT Test Points, that has been developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. Numerous customer beta engagements have shown that EDT Test Points can reduce compressed pattern counts on an average by a multiplicative factor of 2-4X, without affecting test coverage, and even for designs with the most aggressive embedded compression configurations.

Presenter: ThomasRinderknecht, Staff Engineer, D2S DFT R&D Development, Mentor Graphics
DFT (Tessent Product Suite )
  • Delivering SoC Verification in a World of the Internet-of-Things
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    TECHNICAL SESSION IoT interconnect-ness means more verification complexity, more software, low power verification, and time to market pains. We’ll describe how Veloce based verification solution will address the verification of growing design complexities related to the IoT.

Functional Verification and Emulation (Questa Verification Platform; Veloce Emulation Platform)
  • Keynote: Achieving Design Effectiveness
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    TECHNICAL SESSION A design process optimized for speed often just means more ECOs; true effectiveness is achieved with speed AND quality. Quality is achieved by adhering to constraints throughout the design process to produce correct-by-construction designs. Quality also means incorporating a virtual prototyping process that optimizes manufacturability and performance of the end-product. This session will identify critical quality challenges, and an effective design process to address them.

Presenter: A.J. Incorvaia, Vice President and General Manager, Board Systems Division, Mentor Graphics
Products: Xpedition VX
PCB System Design (Xpedition Enterprise)
  • Automotive Simulation Platforms
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    TECHNICAL SESSION Automotive in general and the emergence of new standards and domains, such as AUTOSAR, ADAS and Safety, are breaking traditional design and verification flows as well as Tier I and OEM eco systems and business models. Simulation is a methodology that can address some of these market discontinuities that are also affected by the high cost of failure. We will discuss in this session the specific values simulation offers for designing AUTOSAR systems while tightly integrated into the Mentor AUTOSAR offering.
    We will share some of the AUTOSAR and IVI projects we are engaged with leading customers, as well as looking into the broader automotive simulation vision

BDA / Vista/ P&R (Olympus-SoC)

11:20 AM - 12:05 PM  5 sessions

  • Verify as you go with Calibre Autofix
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    TECHNICAL SESSION Calibre AutoFix performs automatic layout routing correction for place and route designs.
    In traditional place and route flows, verification results are used by physical design engineers to adjust routing geometry in the place and route tool until the errors are no longer present. This verification and rerouting procedure iterates until all errors are corrected, or deemed safe to waive. This can contribute to significant design overhead.
    With Calibre AutoFix, this time-consuming process can be circumvented. When Calibre AutoFix is invoked, it takes the generated verification results from a Calibre® nmDRC™ run and automatically adjusts routing geometry in the layout to correct selected errors.

Physical Verification (Calibre Platform)
  • DFT Technology Seminar – IJTAG Technology – IEEE 1687 | Enabling the ecosystem from chip to system presented by ASSET InterTech and Mentor Graphics
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    TECHNICAL SESSION The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you than legacy probe-based technologies. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips. Don’t miss the chance to learn how to tap into this useful IP. You will have the opportunity to learn from experts from both Mentor Graphics and ASSET InterTech.

DFT (Tessent Product Suite )
  • Customer case studies
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    TECHNICAL SESSION Case study: Productive Software - Hardware debug techniques for pre-silicon SoC level emulation platforms.
    Presenter: Lior Cohen, Broadcom
    Abstract: Policymakers worldwide have set aggressive targets for broadband coverage, challenging governments and service providers alike to connect the world's citizens to the Internet. Fiber solutions (such as GPON\EPON) help meet that challenge, allowing service providers to deliver faster internet access.
    Fiber solutions designs require high speed rates delivered in low-cost implementations for high-volume markets. As a result, the design of Network systems introduces challenges for both design and Software teams. We present the usage of emulation as a key tool in achieving the Fiber design and Software teams targets. Co-verification of HW and SW is usually a joint effort of DV and SW development teams.
    Enabling efficient SW debugging capabilities in pre silicon phase is a key factor for the success of this effort.
    The presentation will describe the usage of CODELINK and Veloce emulator for building a highly productive pre-silicon SoC debug platform.
    Such platform allows debug of real SW code involving both an embedded processor and an external PCIe host.

    Case study: Experience with Large scale SoC Verification Acceleration
    Abstract: User experience of advanced Veloce tools for Verification acceleration.

Functional Verification and Emulation (Questa Verification Platform; Veloce Emulation Platform)
  • Multi-Board System Design with Mentor Graphics Xpedition xSD Systems Designer
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    TECHNICAL SESSION This presentation will introduce Xpedition xSD Systems Designer, including its unique value, key functionality as well as the major benefits

PCB System Design (Xpedition Enterprise)
  • Advances in Nanometer Analog/RF/Mixed-Signal Verification
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    TECHNICAL SESSION The analog, mixed-signal, and RF (AMS/RF) content of semiconductors is growing faster than any time in history, and is at the center of the semiconductor industry’s next major cycle.
    This wave is largely being driven by the rise of nanometer mixed-signal application specific standard products (ASSPs) targeted at new consumer, mobile, automotive, IoT, and datacenter applications. These mixed-signal ASSPs span a wide range of geometries (90nm-14nm) and have significant custom circuit content that push the limits of performance, power, area, and efficiency. The multiple design objectives and complexity of these devices require extraordinary efforts to develop, verify, and get right the first time. Performance targets for PLLs, ADCs, I/O circuits, PHY transceivers, image sensors, and embedded memories are becoming more stringent in the presence of higher device noise, lower supply voltages, less predictable process corners, and ever-increasing parasitics. In the midst of this, designers are being pushed to reduce design and verification schedule with better predictability. This trend is forcing designers to adopt new approaches which will reduce simulation uncertainty in order to close the gap between simulation and silicon and squeeze the most of your silicon for mixed-signal purposes.

    This talk provides an introduction to some of these important proven new approaches that have been successfully deployed in leading design teams to help analyze the effects of a variety of physical and electrical effects- spanning parasitics, coupling, noise, distortion, variability, power etc. - via innovative circuit analysis techniques. Specific case studies will be shown to illustrate the approaches used to target specific problems, and the underlying technology to help achieve this success.

BDA / Vista/ P&R (Olympus-SoC)

12:05 PM - 12:55 PM  5 sessions

  • Working efficiently with the ecosystem of Calibre
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    TECHNICAL SESSION Calibre provides the standard for verification engines. Getting to “done” requires that those engines work with your design flow and your design tools. We will show you how to maximize design productivity with Calibre interfaces into your design tools and how Calibre realtime retains calibre confidence while delivering Immediate results for small scale runs. Case study: Calibre DRV, Calibre Autowaivers and HTML reports

Physical Verification (Calibre Platform)
  • ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 2
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    TECHNICAL SESSION ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 2

    Case study: TestKompress Test Point Insertion
    Presenter: Assaf Gindi, DFT Engineer, Marvell Semiconductor
    Abstract: In modern scan-based testing of semiconductor devices the patterns count is increasing dramatically. ATE test cost also increases as the pattern count increases. This case study describes the results of a successful TestKompress test point insertion evaluation at Marvell Semiconductor. The technology offers automatic insertion of limited control and observe points which reduced pattern count and ATE test cost whilst maintaining coverage.

DFT (Tessent Product Suite )
  • Get Your FPGA Design out of the Lab Faster
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    TECHNICAL SESSION Spending too much time in the lab debugging your FPGA? FPGAs have grown large and complex; so has the task of validating the functionality after it has passed all the tests for area, performance and power. If there is a problem with your FPGA during system integration testing, where do you start looking for issues? This presentation introduces new validation methods to help you instrument your FPGA design so that problems are easier to find as they happen.

Functional Verification and Emulation (Questa Verification Platform; Veloce Emulation Platform)
  • Hyperlynx v9.2  Major Features + case study IAI Elta
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    TECHNICAL SESSION HyperLynx v9.2 is a major release that adds many new features to HyperLynx’s signal - integrity, DDRx,SERDES, and power-integrity simulation capabilities. The release also offers compatibility with Mentor’s latest PCB – design tools and improved integration with the Xpedition VX.1 PCB flow. Case study: Exhaustive SI and PI analysis on technology leadership award winning design Presenter: Itzhak Hirshtsl, IAI Elta, Team Leader Signal Integrity

PCB System Design (Xpedition Enterprise)
  • Vista: Prototyping and Software Enablement
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    TECHNICAL SESSION RTL is running out of steam at the system design level. Higher simulation performance is required to model chips and systems for design exploration and software development before silicon is available. Vista raises the level of design abstraction by utilizing "Transaction Level Modeling" and SystemC. Mentor provides a unique workflow that accelerates system design, partitioning and analysis with the tightly integrated tools for both hardware and software. Vista improves design synergy between system design, embedded software development and design verification. Vista now offers Embedded Virtual Prototype Kits (VPK's), which are out-of-the-box platform models of popular evaluation boards and SoCs from Altera, Xilinx, and Freescale. This reduces customer ramp-up time to effectively use Vista and execute actual embedded software on virtual hardware targets. Vista is complemented by Sourcery CodeBench Virtual Edition, an embedded software IDE for development, debug and analysis. Mentor provides a unique non-intrusive software tracing technology, enabling greater insight into design behavior without altering the embedded software code.

BDA / Vista/ P&R (Olympus-SoC)

12:55 PM - 1:40 PM  1 session

  • LUNCH
ALL DELEGATES

1:40 PM - 2:25 PM  5 sessions

  • Photonics technology implementation with Calibre & Pyxis
Physical Verification (Calibre Platform)
  • ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 3
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    TECHNICAL SESSION ASSET InterTech/Mentor Graphics DFT Technology Seminar - part 3

DFT (Tessent Product Suite )
  • Technology Innovation in Functional Verification - Challenges and Solutions
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    TECHNICAL SESSION This session identifies the emerging common attributes of verification methodology, highlights specific capability enablers for the further optimization of ASIC and FPGA designs verification. The session illustrates how Mentor Graphics’ combines advanced simulation, verification management and SW approach technology to help users exceed their verification goals in time.

Functional Verification and Emulation (Questa Verification Platform; Veloce Emulation Platform)
  • Valor NPI - Integrated DFM
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    TECHNICAL SESSION Ensuring that your PCB designs are optimized for manufacturing just got a lot easier with Valor NPI technology embedded in the desktop of the Xpedition VX release. Valor Fabrication DFM checks can be run by the Xpedition designer at any stage of the layout process, entirely from within the Xpedition user-interface. The latest version of Valor-NPI completes the design validation and final preparation of the manufacturing data for hand-off to fabrication, assembly and test process engineering. You will see how the combination of full DFM analysis before manufacturing handoff plus the use of the new version-8 ODB++ data enable fastest transition to volume manufacturing across multiple manufacturing suppliers.

PCB System Design (Xpedition Enterprise)
  • RealTime Designer & Olympus-SoC: Fastest Full Chip RTL Synthesis and Floorplanning
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    TECHNICAL SESSION One of the predominant RTL synthesis challenges is the capacity limitation and the lack of real floorplanning capabilities of traditional synthesis tools forcing the designs to be broken down into smaller blocks. This divide and conquer approach does not scale well at advanced nodes as the design feasibility is known very late in the cycle. This session will highlight some of the advanced RealTime Designer and Olympus-SoC technologies such as high capacity RTL synthesis, RTL level floorplanning and physical partitioning and design feasibility analysis at the full chip level for handling big designs. The session will also cover benefits of tight integration between the RTL synthesis and physical implementation that leads to faster design convergence and optimal QoR.

Products: Olympus-SoC
BDA / Vista/ P&R (Olympus-SoC)

2:25 PM - 3:10 PM  5 sessions

  • DFM & Smart Fill for advanced nodes with Calibre
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    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Products: Calibre LFD, Calibre YieldEnhancer, Calibre YieldAnalyzer
Physical Verification (Calibre Platform)
  • Customer Case studies presented by Annapurna Labs and Marvell Semiconductor
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    TECHNICAL SESSION Case study:
    Hierarchical ATPG implementation using recursion & hierarchical clock control
    Presenter: Dan Trock, DFT Leader, Annapurna Labs
    Abstract: As the hierarchical ATPG flows become a necessity due to the design size and complexity there is a growing need for less timing- and area- consuming core isolation techniques. Clock control schemes are also required which support a hierarchical test structure as more logic is left outside the wrappers.
    This paper presents a practical implementation of a multi-level hierarchical test flow utilizing a hierarchical clock control design combined with shared style wrapping technique offered by today’s EDA tools.

    Case study:
    Application of Tessent Yield Insight at Marvell, a case study
    Presenter: Michael Degtyar, NP Test and Product Engineering manager, Marvell Semiconductor
    Abstract: Case study – applying Tessent Yield Insight to localize systematic silicon defects and eliminate elevated DC SCAN yield loss.

DFT (Tessent Product Suite )
  • Making Simulation and DSP algorithm talk
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    TECHNICAL SESSION DSP Algorithm development flow requires that the algorithm, often modeled in Matlab, is later implemented in RTL, and that this implementation is verified against the Matlab model. During the RTL implementation and verification phase, Matlab can be used in a variety of roles: as stimuli generator, as a checker, as a model for non-existing parts, or for analysis. All of these roles require, however, that some channel of communication is established between the RTL simulator and Matlab. In this session we will learn about the existing options to pass data to and from Matlab, and discuss their respective merits and shortcomings. We will then present a new solution that is designed to solve some of the shortcomings in existing solutions, and talk about future directions and roadmap for further integration.

Functional Verification and Emulation (Questa Verification Platform; Veloce Emulation Platform)
  • Virtual Highly Accelerated Lifecycle Testing (HALT) for Increased Reliability
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    TECHNICAL SESSION Increasingly complex PCB systems designs with tight electro-mechanical integration are extending physical prototype/test cycles. This session will discuss new technology that delivers fast and reliable virtual prototyping and testing of PCB stress and vibration performance up to 100x faster than tradition physical HALT methodology. This unique solution provides concurrent, upfront virtual simulation to quickly, easily, and accurately detect design problems - even at the component and pin level -enabling multi-discipline teams to meet time-to-market, pproduct quality, and cost-management goals.

PCB System Design (Xpedition Enterprise)
  • ReqTracer - Safety and Requirements Tracing
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    TECHNICAL SESSION This session introduces Mentor Graphics’ ReqTracer, our tool to help manage and automate requirements traceability from specification through design, implementation and verification. We will present an overview of ReqTracer and demonstrate its key capabilities including impact analysis and report generation, and describe how the flexibility of ReqTracer provides tracing of requirements throughout many different tools and engineering flows.

Products: ReqTracer
BDA / Vista/ P&R (Olympus-SoC)

3:10 PM - 3:25 PM  1 session

  • AFTERNOON BREAK
ALL DELEGATES

3:25 PM - 3:40 PM  1 session

  • CLOSING COMMENTS
ALL DELEGATES