TECHNICAL SESSION The analog, mixed-signal, and RF (AMS/RF) content of semiconductors is growing faster than any time in history, and is at the center of the semiconductor industry’s next major cycle.
This wave is largely being driven by the rise of nanometer mixed-signal application specific standard products (ASSPs) targeted at new consumer, mobile, automotive, IoT, and datacenter applications. These mixed-signal ASSPs span a wide range of geometries (90nm-14nm) and have significant custom circuit content that push the limits of performance, power, area, and efficiency. The multiple design objectives and complexity of these devices require extraordinary efforts to develop, verify, and get right the first time. Performance targets for PLLs, ADCs, I/O circuits, PHY transceivers, image sensors, and embedded memories are becoming more stringent in the presence of higher device noise, lower supply voltages, less predictable process corners, and ever-increasing parasitics. In the midst of this, designers are being pushed to reduce design and verification schedule with better predictability. This trend is forcing designers to adopt new approaches which will reduce simulation uncertainty in order to close the gap between simulation and silicon and squeeze the most of your silicon for mixed-signal purposes.
This talk provides an introduction to some of these important proven new approaches that have been successfully deployed in leading design teams to help analyze the effects of a variety of physical and electrical effects- spanning parasitics, coupling, noise, distortion, variability, power etc. - via innovative circuit analysis techniques. Specific case studies will be shown to illustrate the approaches used to target specific problems, and the underlying technology to help achieve this success.