Agenda

LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

KEYNOTE Winning products are rarely the result of optimizing only one aspect of a design. Innovators generate success because they find ways to cross organizational and functional boundaries to optimize a product in multiple disciplines. Mature companies try to solve this problem by creating cross-disciplinary teams while start-up companies do it naturally due to lack of enough resources to allow specialization. Meanwhile, products targeted at customers in different disciplines rarely appeal to more than one. Mentor Graphics has compiled data on cross-disciplinary product successes including attempts by companies to create products for hardware/software co-design, mechanical/electrical design integration and many more. He has identified successes and categorized the ways that companies have (rarely) achieved multi-disciplinary product optimization. He will use these examples to generate some guidelines for companies of all sizes to achieve product development success.

TECHNICAL SESSION Attend this session for an overview of the physical verification, DFM, and extraction solutions being offer by Mentor. The session will highlight the latest features of the Calibre platform and how they are being used by foundry and IP partners to address the issues encountered by designers, including both 2D chip scaling and 3D stacking approaches. The session will also show you how to use Calibre in your design flow to achieve a single sign-off solution regardless of the P&R and custom layout flows or the foundry process you have selected.

TECHNICAL SESSION The upcoming IEEE P1687 standard for IJTAG represents an exciting development. The new standard creates an environment for plug-and-play integration and an easy implementation for embedded test access for IP blocks. IP blocks that can be configured include mixed-signal IPs, self-testable memory and logic BIST blocks. The user does not need know the IP level in the designs, giving a high level of productivity for the IP integrator. Further, IP providers can deliver IPs which can be integrated by third parties.

This presentation offers an overview how Mentor Graphics technology supports the P1687 standard along with usage examples to demonstrate the significant advantages of P1687.

TECHNICAL SESSION There has been a remarkable emergence of new advanced verification techniques, methodologies, languages and new standards in the past ten years. And, recent industry studies have indicated a rapid acceleration in their adoption. This is true across all types of IC design and geographic regions. Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.

Yet, for many projects, the process of evolving their functional verification capabilities presents a paradox. That is, some projects are unable to quantify the effectiveness of these new processes they put in place—or identify opportunities for process improvement—due to the lack of process measurements. As the saying goes, if you can’t measure it, you can’t improve it.

This presentation discusses techniques for evolving SoC functional verification capabilities, from paradox to paradise, with the introduction of metrics-driven processes. A full set of solutions for managing, analyzing, and automating metrics-driven processes will be described.

TECHNICAL SESSION There has been a remarkable emergence of new advanced verification techniques, methodologies, languages and new standards in the past ten years. And, recent industry studies have indicated a rapid acceleration in their adoption. This is true across all types of IC design and geographic regions. Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.

Yet, for many projects, the process of evolving their functional verification capabilities presents a paradox. That is, some projects are unable to quantify the effectiveness of these new processes they put in place—or identify opportunities for process improvement—due to the lack of process measurements. As the saying goes, if you can’t measure it, you can’t improve it.

This presentation discusses techniques for evolving SoC functional verification capabilities, from paradox to paradise, with the introduction of metrics-driven processes. A full set of solutions for managing, analyzing, and automating metrics-driven processes will be described.

TECHNICAL SESSION As product complexity has increased, organizations have been under constant pressure to meet their business drivers while bringing competitive products to the market-place. These pressures are compounded by a significant demographic shift in heritage PCB design and engineering. In the western world, new entrants into the PCB design workplace is in decline, this is happening when engineering graduates as a whole are also in decline. Meanwhile, products are becoming more complex where, what was once isolated processes are now very much integrated. To ensure the viability of the next generation of engineering, there is a drive to lower the barriers to perform core engineering and design activities while enabling organizations to take a systems approach in their development strategies. This keynote will cover these trends and introduce Mentor’s view of integrated systems design for an industry in transition by showcasing specific technologies that will enable next generation of PCB development.

TECHNICAL SESSION Success comes from being at least one step ahead of rivals. What are the challenges that next year will bring and what do you need to know to stay one step ahead?
This presentation explores the challenges that electronic manufacturers will face in today’s quickly evolving environment. Topics to be included:
• Quality requirements in the Internet Age
• Maximizing profit from “hot” products
• Elimination of waste in distribution
• Reducing the true cost of materials

TECHNICAL SESSION Sharon Peretz, Mellanox to discuss issues of DRC on a complex, large, full chip and addressing their requirement for high performance checking.

TECHNICAL SESSION Tessent Shell is a new platform, consolidating all the DFT products. Already available and future features of the platform will ease the life of the DFT engineers. All the DFT implementation will be done within the single platform, having the full TCL support. The design introspection, DRC troubleshouting and coverage improvement will be done within the platform without a need to go out and come back. A TestKompress related example will be reviewed within a presentation.



Case study: Broadcom, Eli Borowitz - Alternative methods for handling BIST multi-cycle paths in ATPG

TECHNICAL SESSION The success of a standard rests on the ability of users to deploy it on their projects. For UVM, that requires tools, infrastructure and training. In this session, we will show how Mentor Graphics, through Questa and the Verification Academy, is providing the resources you need to be productive with UVM. UVM Express is a streamlined view of UVM that gets you up and going quickly to take advantage of constrained-random stimulus and functional coverage. UVM Connect lets you connect UVM and SystemC components to verify transaction-level SystemC designs or to use SystemC components as reference designs in your UVM environment. In addition, Questa provides class-based debug support for SystemVerilog, giving you unparalleled visibility into your testbench and additional Questa features like Verification Management and Intelligent Testbench Automation provide huge gains in your ability to specify, track and ultimately meet your verification goals.

Case study: Rafael, Shay Tsur - Power up verification process with UVM & Questa

TECHNICAL SESSION As many design teams can attest, fast emulation has become a critically important verification component for large and complex systems-on-chip (SoC's). Today, emulation is used to test the hardware aspects of a SoC design and to verify the integration of hardware and the embedded software. It is possible to start RTL verification at the block level and move on to the system level as the entire design takes shape. Emulation can also co-verify the interaction of hardware and software once the full RTL design is complete. In this session, learn about the latest and greatest for the Veloce platform and it’s non-intrusive, software based application’s environment “VirtuaLAB” .

Case study: Broadcom, Yacov Bar Moshe - Multi-node MoCA network emulation

TECHNICAL SESSION The engineering of a complex system of multiple PCBs by a team of engineers requires not only an advanced systems definition capability but also the ability of teams of engineers to define the system and the design constraints concurrently. This session will illustrate Mentor's technology that is unique in the industry where multiple engineers can work on the same schematic and define high speed constraints on a system concurrently while viewing their peers' edits real time. Also the ability to define the multi-PCB system top-down with automated backplane and cable integrity.

TECHNICAL SESSION Surprises cost money, escalate risk and delay execution and in turn constrain business performance and competitiveness. The most successful companies engineer out unknown variability. They use precise engineering tools that quickly and accurately build the manufacturing product model, simulate the production processes and turn fire fighting with customers into collaborative. This presentation shows you how simple it can be and the amazing benefits to be gained as a result.

TECHNICAL SESSION In complex analog design and at advanced nodes, ICs are more sensitive to electrical overstress (EOS) failures and require additional checks that cannot be performed using standard solution as DRC, LVS or ERC. IC designers need new techniques to validate that all required protection structures are in place, and that the complex and special design rules are met.

In this session we will describe a Power Management technology, complex design rules as well as its ESD objectives and challenges, and how it is using Calibre PERC to increase the quality of design and improve long-term reliability. A case study will describe the techniques used, how checks were developed in Calibre PERC and the results achieved.



Case study: TowerJazz, Ofer Tamir

TECHNICAL SESSION With the advent of 20nm, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoC's. At the same time they also face a slew of new design challenges at 20nm that severely impact design performance, power and time to market. Challenges such as double patterning aware placement and routing, DFM, extraction and timing, larger design sizes, stringent low power requirements and process variations have a major impact on design performance and productivity.

This session will highlight some of the key capabilities and differentiators that Olympus-SoC offers to address complex 20nm challenges, and also provides a sneak peak of the product roadmap.

TECHNICAL SESSION Mathworks’ MATLAB® is used to analyze data, develop algorithms, and create models and applications. In the world of electronic system design MATLAB models can be translated into RTL library blocks. The ability to use MATLAB code during the functional verification process significantly reduces the time to develop the verification testbench. Existing MATLAB functions can be used for both the initial testbench development as a DUT before RTL is available, as well as part of a scoreboard to verify DUT functionality.

Within the HDL design community, System Verilog and UVM (Universal Verification Methodology) are being universally adopted for the verification of complex designs. There are many good reasons to link the MATLAB models and UVM testbench environment. The presentation will outline the mechanics of several methods discuss in detail one which the implementation is based on TLM-2.0 (transaction level modelling) standard from the Open SystemC Initiative and UVM-Connect.

TECHNICAL SESSION SoC and System designs are reaching a breaking point with two key related challenges: complex multi-core architectures and software integration. Hardware design is now focused on integrating application, graphics and wireless and I/O sub systems that must be accompanied with proper software layers. This integration and verification effort of hardware architecture, drivers and operating systems, is critical for any silicon delivery, hence must be handled ahead of silicon tapeout. In this session, we will outline how virtual platforms, potentially combined with emulation, can address hardware prototyping, software bring up and system validation in pre-silicon phases, and how they can support performance and power analysis tuned to realistic use cases and real-time applications.

TECHNICAL SESSION Not only are speeds of systems increasing rapidly and now in the multiple Gbps, but the percentage of high speed nets common at over 75%. This all requires extensive analysis and verification during the design process versus producing physical prototypes and testing them in the lab. This session will discuss these required analysis tools in detail for signal integrity analysis of DDRx and SERDES interconnects, Power Distribution Network analysis, the inclusion of 3D SI analysis for via structures, and Analog simulation.



Case study: Rafael, Dror Haviv - HyperLynx simulations in Rafael’s design flow

TECHNICAL SESSION Platforms are a complex integration of multi-discipline designs. Capital* provides a vehicle level perspective on systems engineering at multiple abstractions to transition and assess logical decision into a full vehicle implementation.

* Capital is an advanced software suite for the electrical system & wire harness domain. Used by leading automotive, aerospace and harness makers, Capital is built to support the complex demands of integrated processes from initial vehicle definition through design, manufacture and service.

TECHNICAL SESSION This session will cover how Calibre PEX (ie xRC & xACT3D) addresses the critical challenges of new models for both local interconnect and device-level structures in advanced processes. Topics include
- how to maintain accuracy whilst improving performance, scalability and integration for sign-off.
- managing double patterning, 3D-IC and new TSV models.
- Calibre’s new xACTview to provide more visibility of results.

TECHNICAL SESSION Physical defects, like shorts and opens, may occur during any step of the fabrication process. Well known fault models like stuck-at etc. have proven to be insufficient for today’s technologies that require very low defect (DPPM) rates.

This presentation introduces a new defect-oriented test method called Cell-Aware which takes the layout of standard library cells into account and will explore:
- the Cell-Aware library characterization flow
- an overview of the Cell-Aware ATPG algorithm
- characterization results from a 32nm library
- pattern and coverage results from industrial designs
- production test results from several hundred thousand tested IC’s which show significant reduction of DPPM rates
- cell-internal diagnosis and physical failure analysis results which confirm Cell-Aware tests detect real physical defects

TECHNICAL SESSION Assertion Based Verification (ABV) is a technique to increase the quality and debugability of HDL designs. “Assertions” are fragments of HDL code, added by a design or verification engineer, and appear like a comment in the code but help pinpoint errors, for example, “make sure this never happens here”. Alternatively code fragments can be inserted into HDL code which are “coverage” directives. Coverage directives ensure certain critical states in the design are tested, ie “make sure this happens at least once”. Both PSL and SystemVerilog are languages for implementing assertions and coverage directives.

This session will cover the basics of assertion and coverage directives in VHDL designs. In addition, the session will show how either PSL or SVA, plus off the shelf assertion checkers such as OVL, can be added to VHDL design and testbench, and then simulated and debugged in Questa.

TECHNICAL SESSION Today’s SoC are implementing an increasing number of IP. The quality of these is becoming an increasing problem for SoC designers. Thus, verification environments need to be planned for reusability and high-quality results. Using best-in class verification methodologies, simulation and debugging tools allow to quickly isolate “hard to find bugs” and achieve fast verification closure. Robust random, coverage-driven and assertion-based environments are needed for fast development, debug and exercising corner case scenarios.
This session will give an overview of the Questa Verification Platform and show how it provides a true platform to investigate, analyse and measure your IP verification progress. We will discuss UVM methodology, intelligent TB generation, Emulation, Formal Verification and Verification Management and show how they help to accelerate the process of finding and reproducing bugs, as well as giving the ability to gain visibility into the overall progress of the verification process.

TECHNICAL SESSION PCB systems complexity is increasing at almost an exponential rate. To leverage technology advances and create more competitive products while meeting productivity and time to market goals, requires advanced design technologies as provided only by Mentor Graphics. This session will illustrate some of those technologies such as BGA breakouts, advanced routing, power distribution network design, large system design definition and work-in-progress design data management.

TECHNICAL SESSION Surprises cost money, escalate risk and delay execution and in turn constrain business performance and competitiveness. The most successful companies engineer out unknown variability. They use precise engineering tools that quickly and accurately build the manufacturing product model, simulate the production processes and turn fire fighting with customers into collaborative. This presentation shows you how simple it can be and the amazing benefits to be gained as a result.

TECHNICAL SESSION Mentor’s Calibre DFM solution is ready today to address Litho sign off simulation, advanced fill and other requirements for advanced processes. Come and see the status and roadmap of industry-leading litho friendly design (LFD) and SmartFill technologies, and how you can use them in your design flows.



Case study: Marvell - Yishai Dishon - LFD usage in Marvell

TECHNICAL SESSION One of the paramount decisions during the design process is test pads allocation. The amount of available test pads and their allocation directly impacts test quality and cost. With increased design complexity and reliance on scan compression techniques, it is imperative to optimize compression channels allocation.

Previous TK benchmarking results have shown the potential benefits of using asymmetric allocation of compression channels over a traditional, symmetric one. In those cases, an improvement in pattern count and effective compression was typically achieved by allocating a larger amount of input channels, compared to output channels.

This paper presents an evaluation of various asymmetric channel allocations on an advanced 28nm testcase, where following the path of increasing input channels actually degrades the compression effectiveness. The reasons causing that will be reviewed and an attempt to find a more optimal allocation, which may be applicable to other designs suggested.

TECHNICAL SESSION The adoption of Formal Verification technology has traditionally been encumbered by performance, capacity and ease of use issues. With the Questa Static solution complete SoC designs, greater than 150M gates in size, can now be analysed in a single step. Tens of thousands of assertions for multi-million gate design blocks can now be proven in a matter of hours. Huge strides have been made in advancing the usability of the formal tools, with the development of new features and refinement of methodologies, so that this ground breaking power has been brought to a whole new level of automation.

In this session we will discuss how to eliminate the risk of metastability issues in silicon, automatic formal checks for push-button checking to find functional issues, formal code coverage closure to prune unreachable bins from the coverage model, static X-propagation verification to verify that X-optimism is not masking design bugs and connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections.

TECHNICAL SESSION To realize the benefits of platform-based SoC's, users must be able to develop, optimize, integrate and verify differentiating hardware blocks and the software that defines the final system. Time-to-market and quality are keys to success. Software development and validation must begin on day one to avoid costly schedule delays. Multi-core platforms, with extensible coherent memory, increase the SoC architectural design, integration, verification, and debug challenges. Full system verification and test must begin early in order to adequately test the full breadth and depth of system architecture and performance and deliver the quality that today's market demands.
This session will discuss key features of the Questa Verification Platform and show how to improve SoC verification efficiency by using adjacent technologies such as HW/SW co-verification, emulation, Low Power simulation and formal methods.



Case study: Intel, Claudio Yancu - Accelerated debug with HW/SW coherent debugger

TECHNICAL SESSION The design of today's products requires the collaboration of multiple design team members and multiple development disciplines such as MCAD, ECAD (engineers and layout designers), FPGA and manufacturing. This session will discuss how mentor's unique systems design technologies enable these team members to collaborate real time and reduce their schedules, increase quality and improve productivity.

TECHNICAL SESSION The demand for greater component density on smaller and thinner boards poses significant challenge to the PCB layout process. As a consequence, interconnectivity is denser requiring smaller feature/hole sizes and spaces and, in turn, pushes manufacturers to the limits of their production capabilities. To remain price competitive, manufacturers need to apply layout changes to increase yield and thus reduce manufacturing cost but at the same time maintain electronic design intent.

This session will review the DFM process exercised by the bare board manufacturer. Examples will be used to illustrate how state-of-the art software can optimize board layout for improved yield.

What You Will Learn
- Bare board manufacturer’s pre-production CAM & engineering process, in general
- Typical areas where layout changes can drive higher yield

TECHNICAL SESSION At advanced processes the challenges of lithographic imaging require the use of Double Patterning techniques, which bring new requirements into the design and verification space. This session will take a “deep dive” into the requirements and discuss the methodologies and tool solutions for double patterning exploring the following design aspects: Fix Methodology, P&R, Parasitic Extraction, DFM and Manufacturing.



Case study: TowerJazz - Amir Oren - Calibre Auto Waiver flow – in TowerJazz

TECHNICAL SESSION This session provides attendees with Mentor's product vision, and in depth discussion about our market leading custom IC Design Flow tools. Attendees will receive an introduction and demonstration of our constraint driven custom analog router and Calibre RealTime on-demand signoff design rule checking. The session will conclude with a discussion of Mentor's long term roadmap and strategic technical direction including an update on support for OA based environments.

TECHNICAL SESSION Requirement management and traceability is essential within a safety critical development process such as those used for automotive, medical, aerospace or military projects, but it is equally valuable for any hardware or software based design flow. This session introduces Mentor Graphics’ ReqTracer, our tool to help manage and automate requirements traceability from specification through design, implementation and validation. We will present an overview of ReqTracer and demonstrate its key capabilities including impact analysis and report generation, and take a look at the new features of ReqTracer 2012.1 to manage requirements at a system level. We will describe how ReqTracer fits into a team environment and show how its flexibility can trace requirements throughout many different tools and engineering flows.

TECHNICAL SESSION  Power management is no longer an option.  Studies show that over 50% of the market is already incorporating power management into their SOC and ASIC designs.  For designs that push the envelope in terms of small geometries, the number of companies incorporating power management quickly rises to over 70%.  Mentor has been very active in specifying power management architecture and functionality in terms of verification requirements and solutions, including the delivery of the technology, expertise and leadership which resulted in the IEEE’s Unified Power Format (UPF).  Today, our low power solutions provide comprehensive verification of power managed designs including leading-edge support for UPF2.0.This session will discuss how Questa’s low power solutions can help to comprehensively cover low power management and control.

TECHNICAL SESSION The design of complex PCB systems requires the coordinated efforts of extended design teams as well as leveraging the Intellectual Property of the company such as component libraries and re-usable designs. This requires data management infrastructure that is specifically tuned to the PCB design process. This session will illustrate Mentor's successful capabilities in this area.

TECHNICAL SESSION PCB materials represent ~35% of the overall budget of a volume PCB shop. In the electronic design process, PCB Stackup is defined in general, leaving enough tolerance (~10%) for manufacturing. The customer allowed tolerance on Stackup thickness and impedance values is used by the production process. In addition, thanks to Automatic Stackup simulation tools, the tolerance granted by the customer is also used for cost optimized material selection to reduce the cost of PCB BOM and improve the competitiveness of PCB manufacturer.

This session will review the Stackup optimization process using a unique, multi constraints software algorithm. The algorithm is capable of rapidly simulating thousands of potential Stackups to find an optimal solution which meets the customer requirements.

What You Will Learn
• What are the customer, defined Stackup constraints
• Why designer Stackup definitions cannot be used “as is”
• How InStack ® solves multi-layer HDI Stackup in seconds