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Tuesday, March 25

Tuesday, March 25

8:00 AM - 8:45 AM  1 session

  • REGISTRATION
    Toggle Abstract

    LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

ALL DELEGATES

8:45 AM - 9:00 AM  1 session

  • WELCOME
ALL DELEGATES

9:00 AM - 10:00 AM  1 session

  • Keynote : THE BIG SQUEEZE
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    KEYNOTE For decades, we’ve known it was coming and now it’s here. Moore’s Law—which is really just a special case of the “learning curve”—can no longer drive the 30% per year reduction in cost per transistor, beginning with the 20/16/14 nm generation. Either we find innovations beyond just shrinking feature sizes and increasing wafer diameter or we slow our progress down the learning curve, introducing innovative new electronic capabilities at a slower rate than in the past.
    There are lots of alternatives, including a reduction in profitability of the members of the supply chain, to keep the progress continuing at the same rate as the last fifty years. Dr. Rhines will review the mathematical basis for the dilemma and, with his brand of humor, provide a roadmap of possibilities for the decade ahead.

Presenter: Dr Walden Rhines, CEO & Chairman of the Board, Mentor Graphics
ALL DELEGATES

10:00 AM - 10:25 AM  1 session

  • MORNING BREAK
ALL DELEGATES

10:25 AM - 11:10 AM  5 sessions

  • New design challenges at 28nm and how Calibre addresses them
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    TECHNICAL SESSION Many of you have recently moved from older process technologies to the project that is based on 28nm process. 28nm brings many new hurdles to the physical verification and the parasitic extraction that Calibre can solve. Please join this session and become ready for design work at 28nm!

Physical Verification
  • Test Efficiency is crucial for Time-To-Market while maintaining low DPM
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    TECHNICAL SESSION The DFT engineer is always striving for test efficiency as a key goal but it is continually evolving. The economic pressures are Time to Market (TTM) and reducing or, at least, maintaining a current level of DPM. When technology nodes are changed or there is a new design start which has increasing complexity, performance and low power needs then the established DFT methodologies are challenged.
    Now, each time a new DFT capability or technology is introduced, the DFT engineer gets an opportunity to adapt and improve their test efficiency methodologies. This talk will touch on what today’s leading-edge DFT engineers are implementing and adapting in their test efficiency methodologies.

DFT P&R
  • Veloce - The Cornerstone of SoC Verification
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    KEYNOTE Emulation is no longer a luxury - it is fundamentally an essential part of the SoC verification process. The success of Veloce and its role in increasing the wider adoption of emulation has brought this technology to the forefront of verification methodologies across a range of applications, and is used by leading electronics companies worldwide.   In this session we examine how Veloce’s innovations have created solutions and capabilities that deliver the best-in-class emulation technologies.                                          

Emulation
  • Technology Evolution in Functional Verification: Trends, Challenges and Solutions
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    TECHNICAL SESSION Every two years, the Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. Results of the just-completed survey demonstrate an ongoing convergence of SoC design practices toward a common methodology, independent of the specific tools being used. This type of methodology standardization normally drives the EDA industry into a productive wave of innovation, as EDA companies develop a variety of new tools to optimize results achieved with a standard methodology.
    This session identifies the common attributes of SoC methodology that are emerging, highlights specific capability enablers for the further optimization of SoC design verification, and illustrates how Mentor Graphics’ combines advanced simulation, formal verification, and emulation technology to help you exceed your verification goals

Functional Verification
  • Keynote: Introducing a Major Advance in PCB Systems Design: Xpedition VX
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    KEYNOTE The evolution of Xpedition began in 2005 with the first release of an integrated flow for schematic and layout. In 2007 we met the demands of enterprise IT environments by facilitating client/server architectures. Expedition Enterprise 7.9.x in 2009 expanded mainstream deployment with a highly stable environment. Throughout this journey the industry has come to expect Mentor to deliver leadership innovation for PCB systems design.
    These important milestones have helped us realize our vision to meet the demands of modern development organizations and solidify our leadership in PCB design. Over the months to come, with the Xpedition VX launch, we will continue to deliver solutions that are unmatched in our industry. This is the foundation for the next generation of proven, innovative thinking as we continue to address our enterprise customers’ needs.
    This presentation will address the industry challenges that VX addresses, as well as key release highlights.

Presenter: Henry Potts, Vice President and General Manager, Systems Design Division, Mentor Graphics
PCB System Design

11:10 AM - 11:55 AM  5 sessions

  • Comprehensive Circuit Reliability with Calibre PERC
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    TECHNICAL SESSION Implementing a robust IC verification methodology that addresses circuit reliability is increasingly difficulty for all process nodes. Larger nodes are seeing new challenges that were not apparent in previous generations, such as increasing design complexity. Smaller nodes are seeing greater sensitivity to electrical overstress (EOS), current density and electro-migration issues. For designs with multiple complex power domains, transistor-level power intent verification can be difficult to verify, but new tools are emerging to automate such checking by leveraging UPF. This session describes how Calibre PERC can provide a comprehensive reliability verification platform to address these problems.

Products: Calibre PERC Calibre LVS
Physical Verification
  • Advanced Hierarchical DFT Topics
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    TECHNICAL SESSION SoC designs can implement many variations of a hierarchical DFT architecture and pattern generation techniques including:
    cores embedded in cores, combining wrapped and unwrapped cores and merging top level patterns with core level patterns.
    This presentation will provide an overview of tool capabilities that address these scenarios as well as review how iJTAG can provide greater automation for hierarchical ATPG.

    This presentation includes a case-study

    Title:
    Choosing scan hierarchical flow solution - Dilemmas and considerations

    Abstract:
    The industry trend for emerging size Soc's puts a real challenge on preparing Scan test suite, in many aspects like: ATPG run time, computing resources and test time.
    This presentation will lead us through a testcase from Freescale to realize the difficulty faced on scan suite preparation for a new Soc.
    It will then show how using the scan hierarchical flow (Retargeting) is helping to overcome the obstacles. Preliminary results will be shared.

    Presenter:
    Shlomi Sde-Paz, DFT Manager, Freescale Semiconductor

DFT P&R
  • Delivering a Productive Emulation Platform
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    TECHNICAL SESSION The ability to provide an always-on, productive emulation platform for the high-speed verification of complex SoC’s depends upon the fundamental architecture of the software and hardware employed in next-generation emulators. In this session we examine how Veloce’s emulation SoC architecture, software OS and applications combine to deliver the best-in-class emulation platform, capable of verifying the world’s largest designs, including those with multiple processors and embedded software and across a wide range of applications, such as multimedia, networking, wireless, embedded systems, and storage._x000D__x000D_

Emulation
  • Using standard database techniques for advanced SoC analysis on multiple platforms
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    TECHNICAL SESSION SoC verification has long been considered as a simple extension of block level verification, but is gradually emerging as a distinct domain requiring its own tools and methodologies. Different verification objectives make reuse of coverage models and reference models of very little use, while the difference in size turn platform independence into a crucial requirement. Taking the example of SoC performance verification we will look into the various data sources that are available from SoCs on multiple platforms and at how standard database techniques can operate on those to provide meaningful analysis and visualization.

Functional Verification
  • Unleash the Full Power of your PCB Design Entry Software Tools
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    TECHNICAL SESSION The next major release of Expedition Enterprise will take your PCB Design Entry productivity to the highest level. Come and see how we are making the tool much easier to use for both casual and expert users alike. In addition, we are introducing a new leading edge floorplan-based technology for FPGA on-board optimization. Be one of the first to see live demonstrations of the new industry leading design entry technologies.

Products: DXDesigner, IODesigner
PCB System Design

11:55 AM - 12:40 PM  5 sessions

  • Calibre AutoWaivers Flow
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    TECHNICAL SESSION When verifying a design, certain rule check violations can be waived by the foundry. Such waivers need to be managed in the results output so that they can be preserved for analysis and validation. Inspecting such waivers manually consumes much time. IP vendors can provide IP with waiver information and allow the fabless designer to address only real SOC errors for debugging. The session will show you how Calibre addresses this issue.

Physical Verification
  • Olympus-SoC: Achieving Best Power Performance & Area at Advanced Nodes
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    TECHNICAL SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (28nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC/DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

Products: Olympus-SoC
DFT P&R
  • Pre-Silicon Hardware-Software Debug
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    TECHNICAL SESSION Veloce2 emulation solutions enable RTL designs to be executed fast enough to run software on them well before silicon or development boards are available. But in the past, connections to software debug tools have been slow and unwieldy, resulting in most software developers waiting until development boards are available.  This talk will describe several ways of connecting traditional software debug environments to the Veloce2 emulator with a particular focus to Codelink which has the performance, responsiveness, and features needed to enable software developers to comfortably use Veloce2 emulation solution for early access to designs.

Emulation
  • UVM: Out of Committee into Productivity
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    TECHNICAL SESSION This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.

Functional Verification
  • Multi-Board Systems Design
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    TECHNICAL SESSION The engineering of a complex system of multiple PCBs by a team of engineers requires an integrated set of tools from system-level functional block definition to partitioned PCBs. This session will introduce new technology that provides a single cockpit for all conceptual and logical system definitions, eliminating data re-entry errors and improving system performance.

Products: Systems Designer
PCB System Design

12:40 PM - 1:45 PM  1 session

  • LUNCH
ALL DELEGATES

1:45 PM - 2:30 PM  5 sessions

  • Physical Verification with Multi-Patterning for Advanced Nodes
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    TECHNICAL SESSION Physical verification (PV) complexity continues to grow by leaps and bounds as customers move to the advanced nodes that require multi-patterning. Come learn about the emerging trends in PV and how the Calibre nmPlatform continues to rapidly expand, addressing the needs for advanced PV and helping you get your design to market faster.

Products: Calibre DRC Calibre nmDP
Physical Verification
  • Automotive ATPG: Towards zero DPM and in-system testing
    Toggle Abstract

    TECHNICAL SESSION The growing number of chips in cars and the increasing complexity of these chips has focussed interest in looking for effective DFT methodologies. Due to safety critical requirements coming from automotive standards like ISO 26262, two test goals emerge from them.
    They are a zero DPM requirement and an in-system capability. This talk will discuss the test methodology and test solutions that leading automotive chip providers are implementing today.

DFT P&R
  • Verification:  Innovative Virtual Prototype Technologies for System and Application Bring up
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    TECHNICAL SESSION Embedded Systems designs are transforming to a new world of Virtual embedded SW & HW design. Mentor’s virtual prototyping solution, is revolutionizing the embedded software and hardware design. It offers a tightly coupled hardware & software debug analysis and verification capabilities that are changing the traditional paradigm of HW & SW verification on prototyping boards.

Emulation
  • Verification:  Automate When Possible
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    TECHNICAL SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!

Products: Questa Formal verification, Questa CDC verification, Questa covercheck
Functional Verification
  • Using Accelerated Techniques to Exhaustively Scan Whole PCBs for Potential Problems
    Toggle Abstract

    TECHNICAL SESSION In spite of efforts to make detailed SI and PI simulation as productive as possible, today’s constricted design windows make it difficult to analyze the electrical performance of an entire PCB. How can a designer ensure that no problems “sneak through” into production versions of a board? HyperLynx addresses this need with several automated features requiring minimal modeling and setup, but offering fast verification techniques that make triage of an entire PCB practical. These include accelerated approaches to DC-drop, thermal, crosstalk, and decoupling-capacitor-mounting analysis. Of special note is the new HyperLynx DRC product, a powerful, rules-based verification solution capable of exhaustively analyzing a routed board for common signal-integrity, power-integrity, and EMI/EMC design-guide violations. Out-of-the-box, HyperLynx DRC can rigorously find violations of 22 detailed electrical checks; companies can also author custom rule sets (encrypted, if desired) tailored to proprietary design processes. The DRC product is an exciting addition to the HyperLynx product line — be sure to learn about its unique capabilities in this session.

Products: HyperLynx DRC, including standard and custom rules
PCB System Design

2:30 PM - 3:15 PM  5 sessions

  • DFM at Advanced Nodes
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    TECHNICAL SESSION At 28 nm and below, litho process checking (LPC), CMP analysis and critical area analysis (CAA) are all crucial steps to help ensure manufacturability. In addition, layout fill has become a more complex and critical issue. While in the past the goal was simply to insert minimum fill to maintain planarity, today you need to maximize fill and place and orient it precisely to optimize its benefits. Come to this session to understand today’s DFM issues, to find out what is required by the foundries at each node, to learn about updates to DFM tools, and to see how SmartFill is changing the approach to fill at advanced nodes.

Products: Calibre LFD Calibre YE/YA/YS
Physical Verification
  • Improve Logic Test with a Hybrid ATPG/BIST Solution
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    TECHNICAL SESSION Two test strategies are used to test virtually all IC logic - ATPG with test pattern compression, and logic BIST.
    ATPG has been dominant for years, and is now used for full-chip test across the electronics industry. The growth in ICs for safety critical applications, like automotive and medical, has boosted the demand for BIST. The presentation will deal with a mixture of both – hybrid solution for logic test.

    This presentation includes case-studies

    Case study 1
    Title:
    Isolating Blocks during Scan Testing in a High-Quality Large Industrial Design IP through Wrapper Insertion

    Abstract:
    As the industry has been moving toward large scale SOC designs, the “divide and conquer” strategy gets fundamental for fast scan test suite development and the resulting silicon bring-up.
    This presentation will lead us through the discussion of one of the building blocks of this strategy – isolation of SOC design’s blocks/hard macros. It will then show different wrappers’ insertion options, rules and cost of the implemented solution using the shared wrapper flow.

    Presenter:
    Shahar Ben-Aharon, DFT Manager, AMD Israel

    Case study 2
    Title:
    Using the power of Tessent Shell for quick ATPG rampup

    Abstract:
    Supporting ATPG environment for physical blocks and keeping it updated during design development takes significant time and leads to high overhead on DFT team.
    This presentation describes new method for automatic extraction of ATPG input parameters directly from the netlist.
    This method requires minimal knowledge of input netlist. It is based on Tessent Shell tcl interface and widely uses latest tool commands accessing design objects, collections and netlist attributes.

    Presenter:
    Kostya Korchiomkin, DFT Engineer, Freescale Semiconductor

DFT P&R
  • Applying Veloce2 to Accelerate Verification of Low Power Management and Analysis
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    TECHNICAL SESSION The world of system-on-chips (SoC) is getting smaller, faster, and more power hungry. Yet, from consumer electronics to massive server farms, power consumption must reduce. Consequently, power has become a significant concern for chip designers. This talk explores how Veloce2 complements and extends to the system level the verification task of power management architectures. From the use of the IEEE P1801 Unified Power Format (UPF) standard, to the implementation of comprehensive system-level stimulus environments, Veloce2 offers a complete solution to chip designers for addressing their power verification and analysis concerns.

Emulation
  • Providing Coverage
    Toggle Abstract

    TECHNICAL SESSION The first FPGA Verification session “Providing Coverage” describes code and functional coverage, and how each of these verification techniques can be applied to your verification process. Step by step adoption flows are presented. Answer questions about how coverage can improve FPGA lab productivity. What is the benefit of adding functional coverage? What is the impact of code coverage? How to deploy new processes and manage FPGA project demands. Why does coverage matter and how to leverage FPGA verification process improvements.

Functional Verification
  • Sketch Router:  A Revolutionary New Routing Method
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    TECHNICAL SESSION Should a design be routed manually or with automatic routers? This has been a debate since the advent of auto routing. Most designers prefer manual routing because of their ability to control location of the routes and the quality. Auto routers tend to put in too many vias and often meander unnecessarily which takes considerable time to clean up.

    Quality is objective and subjective. Objective quality means the routing fulfills the signal integrity and manufacturing requirements. Subjective quality means that it looks like manual routing which is usually characterized by minimal vias and trace segments along with unbiased routing (sometimes called river routing). An entirely different approach called the “Sketch Router” enables the designer to control where the routing occurs and provides both the objective and subjective quality desired. This is the biggest advancement in routing technology since routers went gridless.

    This session will discuss the merits of manual routing and demonstrate how the Sketch Router continues that theme and enables the routing task to be unbelievably faster.

Products: SketchRouter
PCB System Design

3:15 PM - 4:00 PM  5 sessions

  • Calibre for Legacy processes
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    TECHNICAL SESSION Communciation around new features and advacend nodes always drive the crowd to the smaller ndoes available. This unfortunately hide the large variety of legacy nodes which are in production today and which also requires advanced techniques to ease the lfie of the designers or the fab engineer. We will concentrate on those so called legacy nodes which by the way are feeding our ecosystem. We will span the large variety of Calibre tools, batch and interactive which allows end users to eprform DRC/LVS checks, debug complicated issues, bring Calibre int eh design environment.

Products: Calibre nmDRC Calibre nmLVS Calibre OPCpro Calibre PERC Calibre Interactive Calibre RVE Calibre DesignRev
Physical Verification
  • DFM-Aware ATPG: A physical layout test methodology
    Toggle Abstract

    TECHNICAL SESSION Silicon defects can occur during the manufacturing process due to certain physical layout structures. Standard ATPG methods are not physically aware and are based on assumptions which are checked using DRC. Further, standard ATPG will optimise the test patterns to reduce tester volume. Thus, standard ATPG cannot always detect some physical defects which are highly prone due to particular layout structures. This talk will describe a methodology which was successfully implemented on customer production designs to significantly improve physical defects.

DFT P&R
  • Creating a Virtual Lab Delivers Higher Productivity in SoC Verification
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    TECHNICAL SESSION Increasing the utilization of hardware emulation resources across multiple teams and geographies is a principal requirement for today’s top electronic companies.  A key enabler for this need is the emergence of software-based or “virtual” emulation environments, where all components associated with an SoC can be modelled in software rather than a mix of hardware and software solutions. VirtuaLAB delivers a fully virtual, block to system level accelerated verification flow for pre-silicon verification of SoCs that have multiple chip interfaces connected to peripherals and host devices. By providing virtual devices for these interfaces, VirtuaLAB delivers ease-of-use and greater productivity while delivering the same functionality as In-Circuit Emulation (ICE).

Emulation
  • Optimizing for Power Efficient Design
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    TECHNICAL SESSION With the explosion of portable electronic devices, designing for low-power is a critical design constraint. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, via automated tools or manually. This session will review how Power Analysis can be done at the RTL level to drive low power optimizations.

Functional Verification
  • Differential Signal Routing for PCB Designers
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    TECHNICAL SESSION The intent of this presentation is to provide PCB layout designers with an understanding of the various concerns when routing differential signals, as well as how to manage the effects. Included is an ordering of the concerns in terms of importance and at which data rates the signal integrity may be compromised. A deep knowledge of signal integrity is not required to benefit from this. There is certainly more depth to each of the conditions discussed; however, we have tried to keep this focused on the routing perspective so PCB layout designers can make the appropriate decisions and compromises to attain successful differential signal routing.

PCB System Design

4:00 PM - 4:30 PM  1 session

  • AFTERNOON BREAK
ALL DELEGATES

4:30 PM - 5:00 PM  1 session

  • CLOSING COMMENTS
ALL DELEGATES