Tuesday, March 25

8:00 AM - 8:45 AM  1 session

  • REGISTRATION
ALL DELEGATES

8:45 AM - 9:00 AM  1 session

  • WELCOME
ALL DELEGATES

9:00 AM - 10:00 AM  1 session

  • Keynote : THE BIG SQUEEZE
Presenter: Dr Walden Rhines, CEO & Chairman of the Board, Mentor Graphics
ALL DELEGATES

10:00 AM - 10:25 AM  1 session

  • MORNING BREAK
ALL DELEGATES

10:25 AM - 11:10 AM  5 sessions

  • New design challenges at 28nm and how Calibre addresses them
Physical Verification
  • Test Efficiency is crucial for Time-To-Market while maintaining low DPM
DFT P&R
  • Veloce - The Cornerstone of SoC Verification
Emulation
  • Technology Evolution in Functional Verification: Trends, Challenges and Solutions
Functional Verification
  • Keynote: Introducing a Major Advance in PCB Systems Design: Xpedition VX
Presenter: Henry Potts, Vice President and General Manager, Systems Design Division, Mentor Graphics
PCB System Design

11:10 AM - 11:55 AM  5 sessions

  • Comprehensive Circuit Reliability with Calibre PERC
Products: Calibre PERC Calibre LVS
Physical Verification
  • Advanced Hierarchical DFT Topics
DFT P&R
  • Delivering a Productive Emulation Platform
Emulation
  • Using standard database techniques for advanced SoC analysis on multiple platforms
Functional Verification
  • Unleash the Full Power of your PCB Design Entry Software Tools
Products: DXDesigner, IODesigner
PCB System Design

11:55 AM - 12:40 PM  5 sessions

  • Calibre AutoWaivers Flow
Physical Verification
  • Olympus-SoC: Achieving Best Power Performance & Area at Advanced Nodes
Products: Olympus-SoC
DFT P&R
  • Pre-Silicon Hardware-Software Debug
Emulation
  • UVM: Out of Committee into Productivity
Functional Verification
  • Multi-Board Systems Design
Products: Systems Designer
PCB System Design

12:40 PM - 1:45 PM  1 session

  • LUNCH
ALL DELEGATES

1:45 PM - 2:30 PM  5 sessions

  • Physical Verification with Multi-Patterning for Advanced Nodes
Products: Calibre DRC Calibre nmDP
Physical Verification
  • Automotive ATPG: Towards zero DPM and in-system testing
DFT P&R
  • Verification:  Innovative Virtual Prototype Technologies for System and Application Bring up
Emulation
  • Verification:  Automate When Possible
Products: Questa Formal verification, Questa CDC verification, Questa covercheck
Functional Verification
  • Using Accelerated Techniques to Exhaustively Scan Whole PCBs for Potential Problems
Products: HyperLynx DRC, including standard and custom rules
PCB System Design

2:30 PM - 3:15 PM  5 sessions

  • DFM at Advanced Nodes
Products: Calibre LFD Calibre YE/YA/YS
Physical Verification
  • Improve Logic Test with a Hybrid ATPG/BIST Solution
DFT P&R
  • Applying Veloce2 to Accelerate Verification of Low Power Management and Analysis
Emulation
  • Providing Coverage
Functional Verification
  • Sketch Router:  A Revolutionary New Routing Method
Products: SketchRouter
PCB System Design

3:15 PM - 4:00 PM  5 sessions

  • Calibre for Legacy processes
Products: Calibre nmDRC Calibre nmLVS Calibre OPCpro Calibre PERC Calibre Interactive Calibre RVE Calibre DesignRev
Physical Verification
  • DFM-Aware ATPG: A physical layout test methodology
DFT P&R
  • Creating a Virtual Lab Delivers Higher Productivity in SoC Verification
Emulation
  • Optimizing for Power Efficient Design
Functional Verification
  • Differential Signal Routing for PCB Designers
PCB System Design

4:00 PM - 4:30 PM  1 session

  • AFTERNOON BREAK
ALL DELEGATES

4:30 PM - 5:00 PM  1 session

  • CLOSING COMMENTS
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