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Thursday, November 07

Thursday, November 07

8:30 AM - 9:30 AM  1 session

  • REGISTRATION
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    LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

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9:30 AM - 9:45 AM  1 session

  • WELCOME
Presenter: Gianluigi Merati, Mentor Graphics
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9:45 AM - 10:30 AM  1 session

  • Keynote : Things Don't Change
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    KEYNOTE Over the last 40 years, electronic has been following and driving some of the most important changes in our society: Initially it served the needs of governments and the military; but today is has percolated down to everyday “things”. This deployment of electronic into our lives and the growing complexity of these interconnected systems increase the pressure for a new engineering approach to solve one of our oldest challenges - electronic systems engineering.
    Mentor Graphics has been working on this topic for decades and is able today to address some of these challenges through our Connected Engineering solutions.

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10:30 AM - 12:30 PM  1 session

  • Panel: Design for Excellence (DFX)
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    LOGISTIC Today's complex system development programs often struggle with late stage problem awareness.
    To produce goods that are low cost, high in quality and best in performance, yet competing on a global landscape, several ingredients are essential like the need to apply cross-functional teams at the early stages of the product development cycle and the strategic application of appropriate tools and virtual prototyping techniques.
    This panel will deal with the DFX context as a disciplined approach and investment in the design phase to drive performance by design, applying innovative methodologies in a structured “proactive” approach key to be successful on the market.

Panelist: Aldo Boschiroli, Head of Digital HW/FW Electronics Engineering, Selex ES – Finmeccanica Group
Moderator: Filippo Fossati, Editor in chief – Technology Division, Fiera Milano editore
Panelist: Liliana Prata, Line Manager PDU Microwave Networks, Ericsson Telecomunicazioni S.p.A
Panelist: Massimo Violante, Prof. associato presso il Dipartimento di Automatica e Informatica del Politecnico di Torino, Informatica del Politecnico di Torino
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12:30 PM - 2:15 PM  1 session

  • LUNCH
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2:15 PM - 3:15 PM  6 sessions

  • Improve design cycle time and achieve design reliability
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    TECHNICAL SESSION As we progress to ever smaller nodes, the number of rule checks keeps growing along with the complexity of the rules. Designers are experiencing more and more iterations, slowing down the convergence to final signoff. The Calibre platform enables to reduce design cycle time and to improve designers efficiency by providing immediate DRC feedback during design and by automating electrical checks for reliability verification. This session describes on-demand, in-design, signoff-quality verification with Calibre RealTime. You will also learn how Calibre PERC can provide a comprehensive reliability verification platform to address electrical overstress (EOS), current density and other advanced ERC issues.

Products: Calibre PERC, Realtime, Interactive, DESIGNrev
IC Design A
  • Eldo: high-performance and high-speed SPICE-accurate simulation
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    TECHNICAL SESSION Come see what differentiates our full SPICE and Faster SPICE high performing simulation solutions. This session will talk about important features including performance improvements of BSIM, PSP and BSIMCMG (FDSOI), new algorithms dedicated to TFT panel simulations, accelerated transient noise analysis with Premier, profiling information for speed bottleneck analysis, and coupled electro-thermal simulation developed in collaboration with ST. We will also show an updated roadmap and the new features added in recent releases

Products: Eldo Classic, Eldo Premier, Eldo RF, EZwave, ICAnalyst
IC Design B
  • ESL Flow: Vista for Architectual Exploration and Virtual Prototyping
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    TECHNICAL SESSION Today’s advanced designs have become too massive and complex for traditional RTL methodologies. Electronic System Level (ESL) design methodologies address this problem by elevating design and verification to a higher level of abstraction, where many engineering tasks and design optimizations can be successfully accomplished more quickly, more efficiently, and more cheaply than at the RTL.

    Vista™ is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping. Vista enables system architects and SoC designers to make viable architecture decisions, and it allows hardware and software engineers to validate their hardware and software early in the design cycle.

    Join this session to learn more about how Vista can help you explore and verify your desing before the RTL stage, establishing a predictable and productive design process that leads to first-pass success.

System Modeling & Embedded Software
  • Providing Coverage
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    TECHNICAL SESSION The first FPGA Verification session “Providing Coverage” describes code and functional coverage, and how each of these verification techniques can be applied to your verification process. Step by step adoption flows are presented. Answer questions about how coverage can improve FPGA lab productivity. What is the benefit of adding functional coverage? What is the impact of code coverage? How to deploy new processes and manage FPGA project demands. Why does coverage matter and how to leverage FPGA verification process improvements.

Digital Design & Verification
  • Sketch Router:  A Revolutionary New Routing Method
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    TECHNICAL SESSION Should a design be routed manually or with automatic routers? This has been a debate since the advent of auto routing. Most designers prefer manual routing because of their ability to control location of the routes and the quality. Auto routers tend to put in too many vias and often meander unnecessarily which takes considerable time to clean up.

    Quality is objective and subjective. Objective quality means the routing fulfills the signal integrity and manufacturing requirements. Subjective quality means that it looks like manual routing which is usually characterized by minimal vias and trace segments along with unbiased routing (sometimes called river routing). An entirely different approach called the “Sketch Router” enables the designer to control where the routing occurs and provides both the objective and subjective quality desired. This is the biggest advancement in routing technology since routers went gridless.

    This session will discuss the merits of manual routing and demonstrate how the Sketch Router continues that theme and enables the routing task to be unbelievably faster.

Products: SketchRouter
PCB System Design A
  • Using Accelerated Techniques to Exhaustively Scan Whole PCBs for Potential Problems
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    TECHNICAL SESSION In spite of efforts to make detailed SI and PI simulation as productive as possible, today’s constricted design windows make it difficult to analyze the electrical performance of an entire PCB. How can a designer ensure that no problems “sneak through” into production versions of a board? HyperLynx addresses this need with several automated features requiring minimal modeling and setup, but offering fast verification techniques that make triage of an entire PCB practical. These include accelerated approaches to DC-drop, thermal, crosstalk, and decoupling-capacitor-mounting analysis. Of special note is the new HyperLynx DRC product, a powerful, rules-based verification solution capable of exhaustively analyzing a routed board for common signal-integrity, power-integrity, and EMI/EMC design-guide violations. Out-of-the-box, HyperLynx DRC can rigorously find violations of 22 detailed electrical checks; companies can also author custom rule sets (encrypted, if desired) tailored to proprietary design processes. The DRC product is an exciting addition to the HyperLynx product line — be sure to learn about its unique capabilities in this session.

Products: HyperLynx DRC, including standard and custom rules
PCB System Design B

3:15 PM - 4:15 PM  6 sessions

  • Calibre for Legacy processes
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    TECHNICAL SESSION Communciation around new features and advacend nodes always drive the crowd to the smaller ndoes available. This unfortunately hide the large variety of legacy nodes which are in production today and which also requires advanced techniques to ease the lfie of the designers or the fab engineer. We will concentrate on those so called legacy nodes which by the way are feeding our ecosystem. We will span the large variety of Calibre tools, batch and interactive which allows end users to eprform DRC/LVS checks, debug complicated issues, bring Calibre int eh design environment.

Products: Calibre nmDRC Calibre nmLVS Calibre OPCpro Calibre PERC Calibre Interactive Calibre RVE Calibre DesignRev
IC Design A
  • Questa ADMS and advanced verification methodologies
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    TECHNICAL SESSION This session will show you how Questa ADMS can extend your Metric driven digital verification methodology across the analog/digital boundary. In this session we will explain how through Questa ADMS you can extend your UVM environment to mixed signal aspects, Power aware (UPF) to mixed signal circuits, and enjoy Questa verification management flow.
    We will feature an example on Analog coverage through analog assertions fully implemented in Questa ADMS.

Products: Questa ADMS
IC Design B
  • Hardware and software design strategies for low power and particularly smart energy devices
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    TECHNICAL SESSION Power efficient Hardware and Software design is a must in today’s society, Smart Medical, Smart Industrial and Smart Energy products require, innovative designs for developing these connected products. These smart devices must be connected seamlessly in an open, standardized, and interoperable fashion. In this session firstly you will learn about how to reduce the power consumption in your design and secondly focusing on the requirements to develop a Smart energy SEP 2.0 compliant device, exploring the strategies you can apply to address the connectivity and security requirements laid out by that specification.

System Modeling & Embedded Software
  • Verification:  Automate When Possible
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    TECHNICAL SESSION In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!

Products: Questa Formal verification, Questa CDC verification, Questa covercheck
Digital Design & Verification
  • Multi-Board Systems Design
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    TECHNICAL SESSION The engineering of a complex system of multiple PCBs by a team of engineers requires an integrated set of tools from system-level functional block definition to partitioned PCBs. This session will introduce new technology that provides a single cockpit for all conceptual and logical system definitions, eliminating data re-entry errors and improving system performance.

Products: Systems Designer
PCB System Design A
  • High-Speed Design
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    TECHNICAL SESSION Virtual prototyping through simulation is critical for today's multi-gbps, SerDes, DDRx, low power designs. We will discuss the latest advances in our simulation tools for signal/power/thermal/EMI integrity, including validation studies that confirmed simulation accuracy at multi-gbps.   

Products: HyperLynx SI/PI/HL 3D with 9.0 and VX content
PCB System Design B

4:15 PM - 5:15 PM  6 sessions

  • Introducing new level of automation to the routing of the OA based analog mixed-signal designs.
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    TECHNICAL SESSION Custom IC design is becoming more complex, with an increasing number of analog mixed-signal blocks and deeper interaction between the digital and analog content. As a result, custom routing using traditional methods has become very time consuming, often taking months to produce a single DRC-clean layout especially at smaller nodes. The Pyxis Custom Router offers a superior routing solution, from transistor to chip level, across all levels of hierarchy. The router is a part of OA based Pyxis Open tool suite that integrates well with Virtuoso. The Pyxis Custom Router offers automated assistance to boost routing productivity, even for non-standard power mesh schemes across multiple power domains in the same AMS cell. The router also helps improve adherence to and compliance with important analog constraints, such as symmetry and shielding while routing both the analog and digital signals. Real cases from different customers show how the Pyxis Custom Router achieved 10x productivity gains and cut months of their overall tapeout schedules.

Products: Pyxis Custom IC Design Platform
IC Design A
  • Olympus-SoC: Achieving Best Power Performance & Area at Advanced Nodes
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    TECHNICAL SESSION One of the predominant place and route challenges is realizing best power, performance and area (PPA), a goal that has gotten significantly more difficult to achieve at advanced nodes (28nm and below). At smaller technology nodes the traditional design closure flow is inadequate due to complex DRC/DFM rules, double patterning requirements, growing design sizes, low power requirements and increasing process and design variations. In addition to solving these challenges, it is also critical to achieve high utilization and reduce the die size to justify the cost of moving to smaller nodes. This session will highlight some of the advanced Olympus-SoC technologies to achieve efficient design closure with unique technologies such as concurrent PPA optimization, pseudo flat flow methodology and DRC/DP signoff during implementation.

Products: Olympus-SoC
IC Design B
  • Multi-discipline, Concept to Implementation Virtual Prototyping
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    TECHNICAL SESSION Today's complex system development programs often struggle with late stage problem awareness, which can arise from document-based processes, isolated development teams, and verification done far too late in the process. This session introduces modern methods for modeling, simulation, and analysis of systems from conceptual-level mechatronics down to the boards that implement them in a multi-discipline virtual prototyping "lab" environment. Using a virtual prototype from the earliest design stages enables powerful verification and collaboration across disciplines (including analog, digital, mixed-signal hardware, software, controls, and mechanical aspects), provides early visibility to bugs, and can reduce overall program cost and risk.

Products: System Vision and SVX
System Modeling & Embedded Software
  • UVM: Out of Committee into Productivity
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    TECHNICAL SESSION This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.

Digital Design & Verification
  • Enabling Enterprise Design Data Management
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    TECHNICAL SESSION The Expedition Enterprise flow is centered on a common design infrastructure between engineering teams, analysis tools and experts, PCB layout, production engineering, and the manufacturing floor. Managing the evolving design data in this environment can be very dynamic, with all of the above data continuously changing. The dynamics of an integrated flow have proven to significantly increase productivity, but also require integrated management of native design data and processes throughout the lifecycle of the design. The complexities of this integrated data set must be clearly understood to accurately move or bundle the design data, or downstream issues can occur and data can become out of sync — leaving you to wonder if you have the right data. We will introduce a new solution (EDM) that addresses both the WIP information management and design data management challenges. EDM provides a centralized environment to manage all the data required to conduct the ECAD design, facilitating collaboration among engineers in real time during the design phase.

Products: EDM (with maybe some DMS updates)
PCB System Design A
  • Lean New Product Introduction
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    TECHNICAL SESSION With the speed of the market today, your product’s success is often determined by the New Product Introduction (NPI) process. How quickly you get your product to market, at what cost and at what quality level is all determined during the NPI process. Mentor’s Valor NPI and Process Preparation software can help you accelerate your NPI process with concurrent DFM and streamlined PCB manufacturing. When coupled with intelligent data exchange via the industry standard ODB++, your supply chain is optimized for efficiency and quality.

Products: Valor NPI, Process Preparation
PCB System Design B

5:15 PM - 5:45 PM  1 session

  • Networking and cocktail reception
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    LOGISTIC Conference close will be celebrated with a cocktail reception offering relaxed networking time.

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