Agenda

LOGISTIC Conference badges for delegates can be collected on arrival. Registration desk will be staffed during this period and breaks.

KEYNOTE Winning products are rarely the result of optimizing only one aspect of a design. Innovators generate success because they find ways to cross organizational and functional boundaries to optimize a product in multiple disciplines. Mature companies try to solve this problem by creating cross-disciplinary teams while start-up companies do it naturally due to lack of enough resources to allow specialization. Meanwhile, products targeted at customers in different disciplines rarely appeal to more than one. Dr. Rhines has compiled data on cross-disciplinary product successes including attempts by companies to create products for hardware/software co-design, mechanical/electrical design integration and many more. He has identified successes and categorized the ways that companies have (rarely) achieved multi-disciplinary product optimization. He will use these examples to generate some guidelines for companies of all sizes to achieve product development success.

KEYNOTE Panel :
1. Pierantonio Palerma - Division Director, Il Sole 24 Ore BusinessMedia (Moderator)
2. Alfonso Fuggetta – CEO of Cefriel
3. Giovanni Sgalambro – VP Change Management and Group CIO – DATALOGIC Group
4. Alessandro Caleo - President EYE-TECH

Notwithstanding the challenging financial climate, some fields are featured by a significant concentration of high-tech innovative activities in line with the diffused opinion that gives credit to Italian entrepreneurs’ creativity and inventiveness. Is commitment to innovation an undisputed catalyst to growth? This panel brings together different experiences and viewpoints of making innovation in high-tech sectors in Italy.

TECHNICAL SESSION What is a system? I am sure that if you ask the question in a room full of engineers you will get as many answers as people in the room. Some are developing system on chips at the nanometer scale, some systems of systems at the kilometre scale and more. If during the past 50 years massive progresses have been made to improve productivity in the IC and PCB design space, system design did not scale as fast with complexity. What do these domains have in common and what are the challenges? How automation can bring solutions to some of these challenges and support system engineers in their need for system optimization, re-use and early validation.

TECHNICAL SESSION Embedded IP comes in a myriad of shapes, forms, sizes, and purposes: controllers for power or clock domains, PLLs, test registers for downstream blocks, Logic and Memory BIST IP, DSPs, sensors, mixed signal blocks and so on. Each one requires specific handling, and integrating all IP access, control, and test requirements is difficult, error-prone, and more often than not a manual process. IEEE P1687 (IJTAG) aims at replacing these ad-hoc methods and proprietary in-house solutions with a structured, universal approach. Following this standard provides full automation of embedded instruments (IPs), true reuse of operations defined at the instrument level, and a safe method of exchanging control, access, or test information for in-house as well as third party instruments.
The presentation outlines what IJTAG is, and how it can help you to get your embedded instrument design done quickly, safely, and first time right.

TECHNICAL SESSION This session explains how Questa ADMS extends digital verification across the analog/digital boundary with AMS debugging, dynamic performance/accuracy trade-offs, analog coverage, analog assertions, UPF and UVM. The UCDB coverage database integrates Questa ADMS in the comprehensive Questa verification management flow. We will also explain this can be combined with the Mentor Faster Spice and Fast Spice solutions (Premier and ADiT) to achieve full SoC mixed signal verification.

TECHNICAL SESSION Android offers a powerful platform for device manufacturers to develop products – be they smart phones, tablets, in-vehicle infotainment or TV type products, etc. Yet it requires stable, well tested, optimized and bench marked Android port for a particular hardware platform. This presentation will discuss how Mentor tools and services can help with porting and optimizing Android platform including key hardware features enablement, graphics and multimedia hardware enabled acceleration, power management and SMP/multi-OS architecture support as well as enabling complete ecosystem for a particular hardware platform. Beyond supporting an Android platform, UI differentiation is a key contributor to the success of an Android device. Given the rise of Android across many products it is essential that device developers find creative ways to differentiate their devices in the market. Creating cutting edge UIs is essential in this quest for device differentiation. Unfortunately creating cutting edge UIs for Android (and Linux) is both difficult and time consuming and often results in fixed UIs which are hard to modify as markets change. This sessions will also presents practical solution for software engineers challenged to create the latest UIs and explores the use of the Inflexion UI platform in solving this UI problem

TECHNICAL SESSION Temperature aware design is now commonplace. Due to ever increasing power dissipation densities, the risks of performance degradation and thermo-mechanical failure are too high to ignore. Mentor Graphics provides a range of tools to serve the needs of electronics cooling design. From package level through board, chassis and final operating environment, our simulation capabilities allow thermally compliant design solutions to be readily identified. The FloTHERM suite of products will be introduced covering their technical capabilities and range of applications that they have been designed for.

TECHNICAL SESSION Requirement management and traceability is essential within a safety critical development process such as those used for automotive, medical, aerospace or military projects, but it is equally valuable for any hardware or software based design flow. This session introduces Mentor Graphics’ ReqTracer, our tool to help manage and automate requirements traceability from specification through design, implementation and validation. We will present an overview of ReqTracer and demonstrate its key capabilities including impact analysis and report generation, and take a look at the new features of ReqTracer 2012.1 to manage requirements at a system level. We will describe how ReqTracer fits into a team environment and show how its flexibility can trace requirements throughout many different tools and engineering flows.

TECHNICAL SESSION The design of complex PCB systems requires the coordinated efforts of extended design teams as well as leveraging the Intellectual Property of the company such as component libraries and re-usable designs. This requires data management infrastructure that is specifically tuned to the PCB design process. This session will illustrate Mentor's successful capabilities in this area.

TECHNICAL SESSION Multi-core, multi-function SOCs in a 3D world require a new set of tools that can get the job done. On the digital side, Calibre xACT-SoC is Mentor's new gate level extraction toolset and contributes to predictable performances of the most critical IC designs while delivering results at lightning speed. Calibre xACT-3D delivers best-in-class accuracy for capacitance extraction with all nets within 5% of reference, even on huge design partitions. The Calibre platform has been extended to support stacked die products, whether they are based on System-in-Package (SiP), silicon interposers or stacked dies with through-silicon vias (TSVs) to answer market demands for miniaturization and higher speeds and bandwidths, as well as lower latency and power.
Finally, Calibre PERC has been designed to address reliability challenges for complex packaged technologies by providing electrostatic discharge (ESD) analysis and multiple power domain checks as well as advanced ERC checks.

TECHNICAL SESSION Come see what differentiates our full SPICE, Faster SPICE or Fast SPICE high performing simulation solutions including, smart Monte Carlo, sensitivity and aging analysis and optimizations for the fastest, most accurate cell characterization. Leading edge support of new FDSOI technology will be presented.We will also show an updated roadmap and the new features added in recent releases.

TECHNICAL SESSION SoC and System designs are reaching a breaking point with two key related challenges: complex multi-core architectures and software integration. Hardware design is now focused on integrating application, graphics and wireless and I/O sub systems that must be accompanied with proper software layers. This integration and verification effort of hardware architecture, drivers and operating systems, is critical for any silicon delivery, hence must be handled ahead of silicon tapeout. In this session, we will outline how virtual platforms, potentially combined with emulation, can address hardware prototyping, software bring up and system validation in pre-silicon phases, and how they can support performance and power analysis tuned to realistic use cases and real-time applications.

TECHNICAL SESSION Semiconductor technology has become the backbone of the electronics industry. With this comes an increased demand to produce efficient, safe and cost-effective solutions that promise a long life-time. In order to do so companies are required to characterize and verify semiconductors from a thermal point of view. Traditional measurement methods only give information of the package temperature or sometimes the die temperature. Thanks to its electrical test method, T3Ster provides extensive information on the thermal structure of a test device in a non-destructive way. The methodology which is now a JEDEC standard and the use of the results will be presented as well as the influence this can have on a decision process.

TECHNICAL SESSION Recent industry surveys show that two-thirds of new design projects fall behind schedule due to verification.  In addition, 70% of these designs fail at least once after verification is completed.  With over half of these failures attributable to logic and functional errors, it makes sense that coverage closure is consistently identified as one of the most difficult challenge faced by verification teams. 

This session will show how Questa can help to gain 10X to 100X in verification productivity by automatically generating SystemVerilog cover groups and Clock Domain Crossing coverage models, reducing nightly regression setup time, automating results merging and coverage analysis and intelligently generating stimulus that achieves target coverage closure faster, and increases overall coverage.

TECHNICAL SESSION Not only are speeds of systems increasing rapidly and now in the multiple Gbps, but the percentage of high speed nets common at over 75%. This all requires extensive analysis and verification during the design process versus producing physical prototypes and testing them in the lab. This session will discuss these required analysis tools in detail for signal integrity analysis of DDRx and SERDES interconnects, Power Distribution Network analysis, the inclusion of 3D SI analysis for via structures, and Analog simulation.

TECHNICAL SESSION This session provides attendees with Mentor's product vision, and in depth discussion about our market leading custom IC Design Flow tools. Attendees will receive an introduction and demonstration of our constraint driven custom analog router and Calibre RealTime on-demand signoff design rule checking. The session will conclude with a discussion of Mentor's long term roadmap and strategic technical direction including an update on support for OA based environments.

TECHNICAL SESSION Olympus SoC offers a comprehensive set of floorplanning and fast prototyping capabilities to address the growing design size challenges at smaller technology nodes.
This session will provide details on the fast prototyping kit based on an ultra-fast placer engine and the new macro analysis engine, that provides a friendly and efficient environment to refine a floorplan, analyze congestion and debug timing constraints. This session will also cover the details on Die creation, pin placement and refinement, macro placement , physical cells placement including power switches, welltaps, endcaps and power grid routing features along with the new GUI environment. UPF based Multi Voltage support for floorplanning will also be addressed.

TECHNICAL SESSION Today’s complex system development programs often struggle with late stage problem awareness, which can arise from document-based processes, isolated development teams, and verification done far too late in the process. Managers also have to deal with the skill sets and flexibility of their people, the tools they use, and how to capture and reuse their knowledge. This session presents an innovative system and design team integration capability featuring SystemVision, Mentor Graphics’ solution for modelling, simulation and analysis of systems from conceptual level mechatronics down to the boards that implement them. SystemVision is a multi-discipline virtual prototyping “lab” environment that enables powerful verification and collaboration across disciplines (including analog, digital, mixed-signal hardware, software, controls, and mechanical aspects), in an integrated design environment. This session will introduce SystemVision in the context of how its being used across a spectrum of Systems development programs in automotive, aerospace, defence, medical and industrial industry segments.

TECHNICAL SESSION An appropriate mechanical structure has become more and more necessary for the proper cooling of an electronic system. Unfortunately the evaluation of the efficiency of the global cooling system usually occurs later in the design process with prototypes already being built. Any failure at this stage can lead to a long and costly redesign process. FloEFD and its Concurrent CFD approach allows the designers to perform thermal and flow simulations inside their CAD environment (Pro/Engineer Wildfire, Creo Parametric, Catia or NX) all along the design process to identify any possible failure as soon as possible. The unique features of the tool, it’s intuitive to use and the wide range of applications where it can be developed.

TECHNICAL SESSION Assertion Based Verification (ABV) is a technique to increase the quality and debugability of HDL designs. “Assertions” are fragments of HDL code, added by a design or verification engineer, and appear like a comment in the code but help pinpoint errors, for example, “make sure this never happens here”. Alternatively code fragments can be inserted into HDL code which are “coverage” directives. Coverage directives ensure certain critical states in the design are tested, ie “make sure this happens at least once”. Both PSL and SystemVerilog are languages for implementing assertions and coverage directives.

This session will cover the basics of assertion and coverage directives in VHDL designs. In addition, the session will show how either PSL or SVA, plus off the shelf assertion checkers such as OVL, can be added to VHDL design and testbench, and then simulated and debugged in Questa.

TECHNICAL SESSION The engineering of a complex system of multiple PCBs by a team of engineers requires not only an advanced systems definition capability but also the ability of teams of engineers to define the system and the design constraints concurrently. This session will illustrate Mentor's technology that is unique in the industry where multiple engineers can work on the same schematic and define high speed constraints on a system concurrently while viewing their peers' edits real time. Also the ability to define the multi-PCB system top-down with automated backplane and cable integrity.