Design & Verification in the SoC Era
San Jose Verification Event
The challenges of verification continue growing exponentially. Through advances in technology and methodology, verification productivity has improved dramatically over the past decade. Yet, the continuing growth in the size of verification teams and the amount of project time dedicated to verification indicate the need for greater advances in productivity.
As we enter the era of SoCs, verification complexity will be driven by increased design complexity of multiple cores running many applications to deliver on-demand content in consumer devices such as tablets and smartphones.
It is clear that verification must be transformed in order to deliver the productivity that will enable the next generation of multi-core SoC consumer electronics. Innovative technologies that deliver 10-100x advances in verification are required. As the impact of software in electronic systems grows, verification solutions must expand to enable co-verification with advanced verification technology. Comprehensive solutions and methodology will integrate these innovative tools and enable real-time progress tracking, trend analysis and increased automation and efficiency of the verification process.
Event Overview
Attend this seminar to learn how you can dramatically boost productivity, radically decrease time-to-coverage, and more effectively and efficiently manage your verification processes from transactions to transistors.
Event Highlights
- Learn more about the latest Technology and Design solutions with multiple technical sessions and tracks
- Attend keynote sessions delivered by Harry Foster and John Goodenough
- Take the opportunity to share experiences and network with your peers
Who Should Attend
- Design and Verification Engineers and Managers
Location Details
DoubleTree by Hilton Hotel San Jose
Tuesday, October 18, 2011
DoubleTree
by Hilton Hotel San Jose
2050 Gateway Place
San Jose, CA 95110
ph: 408.453.4000
fax: 408.437.2898
Featured Presenter
Event Partners
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