Event Highlights
Keynote: ARM, John Goodenough
John Goodenough
ARM
Challenges of Design & Verification in the SoC Era
Harry Foster
Mentor Graphics
Abstract: Just as ASIC complexity drove the innovation and adoption of RTL synthesis, constrained-random testing, assertion-based verification and functional coverage, the SoC era is driving innovations in design and verification. What defines the requirements for the SoC era? What is the future of design and verification for SoCs?
Lunch Panel: The Future of Active Power Management and the use of IP in Power-Efficient Design and Verification
Abstract: Customer demand is forcing semiconductor companies to produce more power-efficient products while at the same time technology constraints are making power reduction even more challenging. Panelists will discuss where they see the future heading with regards to power management and its impact on design and verification and the role and needs surrounding power-aware IP in that process.
blogs
Part 1: The 2012 Wilson Research Group Functional Verification Study
Design Trends
In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide…View Blog Post
Those nasty wire’s and reg’s in Verilog
A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s…View Blog Post
Getting AMP’ed Up on the IEEE Low-Power Standard
Power Aware Verification Course Modules Released
I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns…View Blog Post