FPGA Advantage

Duration

3 days

Pricing

1.950 EUR

Description

FPGA Advantage training will help you acquire the skills needed to maximize your usage of FPGA Advantage and improve your FPGA design process. This course will teach you how to create custom designs from concept to silicon. The lecture modules will demonstrate the FPGA Advantage design flow from the basics of creating a graphical design in HDL Designer Series, through verifying your design in the ModelSim® HDL simulator, to synthesizing and optimizing your design into a physical device with Precision RTL. Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
 

You will learn how to

• Build conceptual HDL designs quickly using HDL Designer Series
• Build HDL state machines, block diagrams, truth tables, and flow charts
• Debug and verify your conceptual design using ModelSim®
• Create test bench designs quickly
• Synthesize your HDL design into a wide range of physical FPGAs using Precision RTL
• Optimize your design for speed and area
• Use hierarchical designs effectively
• Perform static timing analysis
• Use top-down and bottom-up design techniques
• Use pre-defined macro functions, IPs and vendor specific macro generators
• Reuse design elements
• Perform gate level verification, compare waveforms against RTL simulation

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using FPGA Advantage under the guidance of our expert instructors. Hands-on lab topics include:
 

• Set-up design flow and design data structures
• Place existing design elements into new designs
• Create HDL design units, block diagrams, state machines, truth tables, and flow charts
• Create control logic using state machines
• Test your design interactively
• Synthesize designs quickly using Precision RTL's task bar
• Create a test bench using flow charts
• Troubleshoot designs graphically using state machine animation and history tracking
• Use VHDL Generics to parameterize designs
• Synthesize and optimize designs for speed and/or area
• Perform static timing analysis on synthesized designs
• Perform gate level verification, compare waveforms against RTL simulation

Audience

• FPGA Designers
• CAD Engineers and Managers who will be responsible for integrating FPGA Advantage into their design flow
• Members of CAD support groups who are responsible for increased productivity of FPGA design teams

Prerequisites

• Basic knowledge of FPGA and hardware design techniques and procedures
• Reading knowledge of HDL languages (VHDL or Verilog)

Key Topics

• Understanding the FPGA Advantage design flow
• Understanding design data organization
• Using HDL Designer's Design Browser
• Using On-line help
• Block Diagrams - What they are and when to use them
• Creating, editing, and saving Block Diagrams
• Routing signals
• State Machines - What they are and when to use them
• Creating, editing, and saving State Machines
• Working with State Machine Transitions
• Setting State Machine Signal Status
• Generating HDL from an HDL Designer's design
• Testing designs interactively using ModelSim®
• Compiling HDL for ModelSim and Precision RTL
• Using the ModelSim User Interface
• Creating, simulating, and reusing stimulus
• Basic ModelSim troubleshooting techniques
• Basic synthesis using Precision RTL
• Preparing a design for synthesis
• Using the Precision RTL User Interface
• Synthesizing using Quick Setup
• Viewing the results of synthesis
• Choosing the right State Machine
• Controlling State Machine output with Signal Status
• Using Test Benches
• Converting blocks to components
• Creating, editing, and saving component symbols
• Auto-generating test bench components
• Flow Charts - What they are and when to use them
• Using concurrent Flow Charts
• Controlling and viewing simulation from HDL Designer's design windows
• Troubleshooting simulation with animation and crossprobes in HDL Designer Series
• Using Generics to create configurable designs
• Adding HDL statements and declarations to designs
• Using Flow Tabs in Precision RTL
• Selecting a target technology
• Setting timing constraints
• Optimizing designs for area
• Using a top-down design methodology
• Creating, editing, and saving Truth Tables
• Advanced simulation techniques
• Debugging critical paths in synthesized designs
• Synthesizing hierarchical designs
• Optimizing for speed
• Static Timing Analysis