Questa Essentials

Duration: 2 Days
Price:  1.300 EUR
Part Number:  223971

Description

The Questa Essentials course is designed to teach you the benefits of QuestaSim’s advanced verification environment. Lectures include advanced functional verification topics such as constrained-random stimulus generation, functional coverage, code coverage, and SystemVerilog assertions. Additional topics include Advanced Verification Methodology (AVM), Direct Programming Interface (DPI), Power Aware verification, and transactions. Students also will learn how to use QuestaSim’s integrated Verification Management technology, comprising of a verification plan, the Unified Coverage Database (UCDB), test tracking capabilities, ranked test results, and generated HTML reports.

Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

You will learn how to

• Create a Verification Plan
• Perform “Code Coverage” on a design
• Debug SystemVerilog Assertions in the GUI
• Create constrained random simulation environments
• Debug conflicting constraints
• Create and save different verification runs in the UCDB
• View covergroups, assertions, and cover directives in the GUI
• Debug SystemVerilog Assertions in the Assertion Thread Viewer (ATV)
• Import a test plan into the Verification Management Test Browser
• View and track the Test Plan and regression tests in the Test Tracker window
• Merge regressions tests and rank them
• Find and fix unlinked test items in the Verification Plan
• Experiment with QuestaSim’s advanced debugging capabilities
• Call a “C” function from SystemVerilog through DPI
• Use QuestaSim’s Power Aware functionality
• Use commands to facilitate performance and debugging
• Create and record SystemC and SystemVerilog transactions
• View transactions in the GUI

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using QuestaSim software. Hands-on lab topics include:

• The Verification Plan
• Code Coverage
• Debugging SystemVerilog Assertions
• Debugging a failure in the constraint solver
• Verification Management
• Debugging
• DPI
• Power Aware
• Vopt and performance
• Transactions

Audience

Design and verification engineers looking to upgrade their verification knowledge and process

Prerequisites

• Familiarity with SystemVerilog and C recommended
• VHDL and Verilog

Key Topics

• The Verification Plan
• Verification trends
• Verification Management goals
• Advanced Verification Methodology (AVM)
• Verification Management: The ideal process
• Verification Management: Components of a good verification plan
• Verification Management: Creating the Verification Plan
• The Unified Coverage Database (UCDB)
• Importing the Verification Plan into the Test Browser
• Merging saved test runs (verification data) with the Test Plan
• Code Coverage
• Purpose of Code Coverage
• Types of Code Coverage
• Code Coverage in the Workspace
• Instance Coverage
• Code Coverage in the MDI window
• Missed Coverage and Details
• Code Coverage in the Objects window
• Finite State Machine3 (FSM) coverage in the GUI
• Excluding lines and files from Code Coverage
• Saving, reporting and reloading coverage data
• Enabling Code Coverage in Questa
• Functional Coverage: what is Functional Coverage
• Enabling Function Coverage in Questa
• Cover directives, covergroups and assertions
• Viewing Functional Coverage in the GUI
• Assertion-Based Verification: SystemVerilog Assertions
• Assertions in the GUI
• Active threads and capturing transient data
• SystemVerilog and VHDL bind
• Random stimulus
• Directed versus random testing
• Object based randomization
• Different types of constraints
• Functions in constraints
• Pre and post randomization
• The solution space
• The constraint solver
• Randomization commands
• Verification and coverage metrics
• Creating the test environment
• Post simulation analysis and debugging
• Stored attributes in the UCDB
• Viewing coverage statistics in the Test Browser
• Rank coverage to determine test contribution
• Questa Verification: Test tracking
• Finding and fixing unlinked coverage problems
• Generating HTML reports
• Questa advanced debugging features
• Direct Programming Interface (DPI)
• Questa Power Aware verification
• Separating Power Aware specifications from functional specifications
• The Power Control Format (PCF) file
• PCF: What needs to be specified
• Power Aware usage model
• Vopt and performance
• 3- 2- and 1-step vopt method
• Preserving visibility
• Global optimizations
• Black box flow
• Performance profiling
• SystemC and SystemVerilog transactions: coding and recording