VHDL Introduction
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Course Part Number: 230366
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Course Overview
This course is intended for designers who are new to VHDL and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
You will learn how to
- Avoid the common mistakes people make when first using VHDL
- Correctly model sequential and structural VHDL
- Write synthesizable RTL design descriptions
- Structure and create testbenches to verify your RTL code
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using the ModelSim simulator and the Precision Synthesis tool. Hands-on lab topics include:
- Code synthesizable combinational and sequential logic blocks
- Write a complete testbench
- Code a synthesizable RTL State machine
Prerequisites
Familiarity with concepts of verification
Key Topics
Link to Student Workbook:
TOC.pdf