VHDL Introduction
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Duration: 4 days
Pricing: 2,600 EUR
Course Part Number: 230366
Description
This 4-day course is intended for designers who are new to VHDL and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
You will learn how to
- Avoid the common mistakes people make when first using VHDL
- Correctly model sequential and structural VHDL
- Write synthesizable RTL design descriptions
- Structure and create testbenches to verify your RTL code
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using QuestaSim simulator. Hands-on lab topics include:
- Code synthesizable combinational and sequential logic blocks
- Write a complete testbench
- Code a synthesizable RTL State machine
Audience
Design and Verification Engineers interested in VHDL
Prerequisites
Familiarity with concepts of verification
Key Topics
- Simulation Environment
- VHDL Grammar
- VHDL objects, data types and operators
- Design units and the logic packages
- Concurrent VHDL
- Sequential VHDL
- Structural VHDL
- Writing testbenches
- Finite State Machines
Related Courses
HDL Training PartnerThis course is developed and delivered by Willamette HDL. Founded in 1993, WHDL instructors are experts in Verilog, VHDL, SystemC and SystemVerilog.