SystemVerilog Open Verification Methodology (OVM)

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Duration: 3 Days
Pricing: 1.950 EUR
Course Part Number:  231919

Course Overview

This 3 day course is for engineers interested in developing SystemVerilog verification environments using the Open Verification Methodology (OVM).

First the student will learn Transaction Level Modeling (TLM) modeling and communication and basic Testbench structure with various strategies for connecting to the DUT and analysis pieces such as scoreboards and coverage collectors. Then the student will learn about writing reusable and flexible testbenches using the class factory, hierarchy, and configuration and managing test cases using sequences.

The course is a consistent mix of lecture and lab-exercises.

YOU WILL LEARN HOW TO

• Develop basic OOP based testbenches using TLM Interfaces and other OVM library base classes
• Develop testbenches with either TLM or RTL target devices
• Stimulus generation using constrained randomization
• Develop reusable and flexible testbenches
• Develop analysis components – scoreboards & coverage collectors
• Create reusable verification IP (VIP)
• Score boarding using functional coverage and other techniques
• Learn techniques for managing test cases

HANDS-ON LABS

Throughout this course, extensive hands-on lab exercises provide you with practical experience using QuestaSim software and the OVM library.

AUDIENCE

• Verification Engineers

PREREQUISITES

• SystemVerilog for Verification training course or equivalent SystemVerilog experience

KEY TOPICS

Introduction to OVM

Transaction-level Communication

• TLM Channels
• Port & Exports

Basic Testbench Structure

• Test as top
• Components
• Phases
• Environment
• Starting/stopping tests

Dynamic Construction - Introduction to the OVM Class Factory

Connecting to the DUT

• Transactors
• Virtual Interfaces

Generating Reports and Messaging

• Reporting API

Modeling Transactions

• Transaction API

Adding Analysis Components

• Analysis components
• Scoreboards
• Coverage Collectors

Hierarchy

• Hierarchical API
• Port connections

Creating a Configurable Test Environment

• Test as Top Level Class
• Factory Overrides
• Configuration

Sequences

• Simple
• Complex

Other OVM Classes

Reference Topics

• Using SystemC TLM models in a SystemVerilog Test Environment
• Design Patterns

Related Courses

• SystemVerilog for Verification