HDL Designer Series

English Version

Dauer: 2 Tage
Preis: 1.300 EUR
Partnummer:  209128

Beschreibung

Das Tool HDL Designer ermöglicht dem Anwender ein digitales Design graphisch zu erfassen und aus dieser Graphik den entsprechenden VHDL oder Verilog Code automatisch zu generieren. Desweiteren verfügt HDL Designer über Designmanagement Funktionalitäten, die es dem Anwender ermöglichen aus HDL Designer den kompletten HDL Design Flow bis hin zum Place & Route zu verwalten. Der Teilnehmer erlernt sämtliche Möglichkeiten der graphischen Eingabe. Die Übungen führen von der Eingabe über die HDL Generierung und Kompilation bis zur Simulation, Synthese, Place & Route und der abschliessenden Gatelevel Simulation. In einer weiteren Übung wird die Animation von Zustandsmaschinen und Flußdiagrammmen gezeigt.

Inhalt

Teilnehmer

Hardware-Entwickler, die ein Design graphisch beschreiben und daraus VHDL/Verilog Code generieren möchten.

Voraussetzungen

• Englisch Kenntnisse
• Windows-Grundkenntnisse
• VHDL oder Verilog Grundkenntnisse

Dauer: 2 Tage
Preis: 1.300 EUR
Partnummer:  209128

Description

The HDL Designer course was developed to teach you to use HDL Designer Series effectively in your FPGA or ASIC design process.  The lecture takes you through the HDL Designer Series design flow.  This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors. 

You will learn how to

• Set up libraries to hold your designs
• Model hierarchy and connectivity using block diagrams and IBDs]
• Model finite state machines with state diagrams
• Model sequential processes with flow charts
• Model combinatorial circuits with Truth Tables
• Create and edit component symbols
• Generate HDL for your graphical/textual design
• Compile your design for simulation
• Simulate your design using ModelSim
• Animate and debug your design
• Reuse components
• Convert existing HDL designs into graphical/textual HDL Designer Series designs
• Create test benches
• Manage your design using version management
• Interface with a wide range of downstream tools (compilers, simulators, and synthesis tools)

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using HDL Designer Series software. 

• Import existing HDL code into HDL Designer
• Create block diagrams, state machines, truth tables, and flow charts
• Create control logic using state machines
• Generate HDL for your design
• Create a test bench using a flow chart to provide stimulus
• Compile and simulate your design
• Troubleshoot your design using animation
• Place existing design elements into new designs
• Import existing HDL code into HDL Designer Series
• Use Version Management to manage your design objects

Audience

• FPGA and ASIC Designers
• CAD Engineers and Managers who will be responsible for integrating HDL Designer Series into their design flow
• Members of CAD support groups who are responsible for increased productivity of FPGA and ASIC design teams

Prerequisites

• Basic knowledge of FPGA and ASIC and design techniques and procedures
• Reading knowledge of HDL languages (VHDL or Verilog)
• Familiarity with Windows 98, NT, 2000, XP or UNIX operating systems

Key Topics

• Understanding the concept of libraries, design units and views
• Understanding library mapping
• Understanding the HDL Designer Series design flow
• Using HDL Designer Series's Design Browser
• Traversing a design
• Using On-line help
• Block Diagrams - What they are and when to use them
• Creating, editing, and saving Block Diagrams
• Instantiating HDL Designer Series components
• Instantiating external IP components
• Routing signals
• Ripping buses
• Autorouting signals
• Using port map frames
• Using GENERATE frames
• State Machines - What they are and when to use them
• Creating, editing, and saving State Machines
• Working with State Machine Transitions
• Setting State Machine Signal Status
• Using hierarchical state machines
• Using concurrent state machines
• Generating HDL from a HDL Designer Series design
• Testing designs interactively using ModelSim®
• Compiling HDL for simulation with ModelSim
• Using the HDL Designer Series interface to ModelSim
• Controlling and viewing simulation from HDL Designer Series design windows
• Troubleshooting simulation with animation and crossprobes in HDL Designer Series
• Using Test Benches
• Converting blocks to components
• Creating, editing, and saving component symbols
• Auto-generating test bench components
• Flow Charts - What they are and when to use them
• Using hierarchical flow charts
• Using concurrent Flow Charts
• Using Generics to create configurable designs
• Adding HDL statements and declarations to designs
• Creating, editing, and saving Truth Tables
• Compiling designs for synthesis tools such as Leonardo Spectrum and Design Compiler
• Design management using version control
• Importing existing HDL into HDL Designer Series using HDL Import
• Importing HDL Designer Series graphics into documents using OLE (Object Linking and Embedding)