PSL: Assertion Based Verification with Questa

Dauer: 2 Tage
Preis: 1.300 EUR
Partnummer:  220913

Description

This class introduces you to the concept of Assertion Based Verification (ABV), and also gives you the tools to start using the techniques in your design and verification tasks. It covers an introduction to the PSL language, Accellera Version 1.1, so that you can write the properties and assertions for your code, and also considers simulating with the assertions using Questa and it's Assertion capabilities. It shows how Questa's assertion capabilities combine with its other aspects to help you debug your design efficiently. 

In addition the course will explore Functional Coverage: what it is, why it is needed and how the PSL cover directive can be used when measuring it. This will be shown practically using the Functional Coverage capabilities in Questa. 

Finally the changes made in the language with the IEEE 1850 release are briefly reviewed.

The Hands-on labs will reinforce the lectures, providing you with the chance to specify ‘real' properties in PSL, and experience using the tool to simulate what you have written, under the guidance of our expert instructors.

You will learn how to

• Apply the process of assertion based verification.
• Use the PSL Language including:
  -          PSL Layers
  -          PSL Flavors
  -          Boolean Expressions and operators
  -          Sequences (SEREs) and operators
  -          Properties, and property operators
  -          Directives
  -          V units
  -          Some Coding Guidelines
• Compile PSL in Questa
• Simulate with PSL in Questa including:
  -          Use of the Assertion Window
  -          Assertion Commands
  -          Debugging with assertions, using other Questa Windows.
• Measure Functional Coverage:
  -           The PSL Cover Directive
  -          QuestaFunctional Coverage Windows and commands

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using PSL within QuestaSim under the guidance of our expert instructors. Hands-on lab topics include:

• Write assertions to verify basic operation of a design.
• Use QuestaSim to simulate and debug the assertions written in the previous lab
• Write and debug more complex assertions, and use them to verify a design
• Identify cover points, instrument a design for coverage and simulate it. 

Audience

• Verification Engineers
• FPGA and ASIC Designers
• System Designers who wish to use PSL Assertions as part of their specification of lower level functionality

Prerequisites

• Basic knowledge of FPGA/ASIC design techniques and procedures
• Basic knowledge of VHDL or Verilog
• Experience using the Questa simulator for traditional HDL dynamic simulation.

Key Topics

• Verification Trend
• Assertion Based Verification – What is it?
• Open Verification Library – OVL
• History of Property Specification Language (PSL)
• Assertion Versus Property
• What Properties are Written About
• PSL Language Structure Pyramid
• PSL Flavors
• Boolean Expressions
  -          Clock Expressions
  -          Defining a Default Clock
• Temporal Layer
  -          Sequences
  -          Sequence Operators
  -          Properties
  -          Boolean Implications
  -          Sequential implications
  -          Property operators
• Verification Layer
  -          Directives
• Recommended Use
• PSL Embedded in VHDL Code
• V units
• Modeling Layer
• Using PSL with Questa
  -          Compiling
  -          Simulating
  -          Assertion Simulation requirements
  -          Assertion Browser Window and it’s settings Dialogs
  -          PSL Debug Process in Questa
• Clocks and Clocked SEREs.
• Named Sequences
• More Sequence operators: Fusion, OR, Non-Matching and Matching
• Named Properties
• Strong vs Weak Operators
• Property Operators families: next, next_a, next_event_a, next_event_e, before, until, whilenot, within
• Logical Property Operators
• Safety vs Liveness
• Clocked Properties
• %for and %if Constructs
• Built-In Functions
• General PSL Coding Guidelines
• Background to Functional Verification
• Identifying cover points
• The cover directive
• Using PSL and Functional Coverage in Questa
  -          Compiling
  -          Simulating
  -          Functional Coverage Windows.
  -          Functional Coverage Flow
  -          Understanding Functional Coverage Results
  -          Weighting
• Guidelines on using cover directive
• Examples of ABV methodology in use