0-In Assertion Synthesis
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Dauer: 1 Tag
Preis: 650 EUR
Partnummer: 223511
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Course Overview
The 0-In Assertion-Based Verification (ABV) course is for engineers interested in deploying an assertion-based verification (ABV) methodology. The primary focus is on methodology, i.e. why, where, when, and how to add assertions to your design to improve verification quality. It provides an introduction to assertion languages (SVA, PSL) and assertion libraries (OVL, QVL), and will cover how the three verification techniques, simulation, formal verification, and hardware assisted verification techniques use assertions to improve the verification quality.
Through hands-on labs you will be taught how to instantiate, simulate and debug with assertions mainly with OVL and QVL components in the Questa simulation environment. You will see how these assertion libraries and methodologies will help detect bugs earlier in your design flow and improve your overall design quality.
You will learn how to
- Execute on an ABV methodology to increase your design & verification quality
- Introduction to assertion languages (SVA, PSL) and assertion libraries (OVL, QVL)
- Assertion Methodology Recommendations
- Implementing your verification plan with assertions
- Who should add assertions and for what purpose
- Where & when to add assertions
- Utilize OVL and QVL libraries in simulation
- Instantiating and compiling assertion library components
- Simulating & debugging with OVL & QVL
- Viewing coverage
Hands-on Labs
The Hands-on labs will emphasize the lecture concepts, providing you with the practical experience of instantiating, simulating and debugging OVL and QVL library components in the Questa environment. Hands-on lab topics include:
- Instantiate QVL monitor to check AMBA interface
- Instantiate OVL/QVL checkers to check design structures
- Simulate and debug assertion library components with QuestaSim
- Generate and view monitor and checker coverage
Audience
- Design Engineers
- Verification Engineers
Prerequisites
- Basic knowledge of VHDL or Verilog
- Familiarity with HDL simulation
Key Topics
- Introduction
- What are SVA, PSL, OVL and QVL?
- Assertion Methodology Recommendations
- Instantiating and Compiling OVL/QVL
- Debugging, Viewing Coverage and Troubleshooting
- OVL and QVL Assertion Examples
- QVL Monitor Examples