Verilog Fundamentals for SystemVerilog
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| Date Begins | Date Ends | Time | Location | Register |
|---|---|---|---|---|
| Jul 28, 2008 | Jul 28, 2008 | 9:00am - 4:00pm | Munich | Register |
| Sep 29, 2008 | Sep 29, 2008 | 9:00am - 5:00pm | Munich | Register |
| Nov 17, 2008 | Nov 17, 2008 | 9:00am - 5:00pm | Munich | Register |
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Dauer: 1 Tag
Preis: 650 EUR
Partnummer: 226904
Beschreibung
This 1 day class is a prerequisite for engineers who wish to take the SystemVerilog for Verification course but do not have a Verilog background. It will provide a basic understanding of Verilog so the student can utilize SystemVerilog for design verification.
Special emphasis is placed on the event queue, blocking and non-blocking assignments and other language underpinnings that are maintained and extended in SystemVerilog.
You will learn how to
- Write and understand basic Verilog code
- Describe the basic workings of the Verilog scheduler with event queues, blocking and non-blocking assignments
Audience
Verification engineers planning to use SystemVerilog for their Hardware Verification Language (HVL) who do not already know Verilog.
Prerequisites
- Familiarity with concepts of simulation
- Familiarity with Windows 98, NT, 2000, XP or UNIX operating systems
Key Topics
- Introduction to Verilog
- Basic modeling structure
- Lexical conventions
- Modules
- Port declarations
- Module instances
- Data types
- Procedural blocks
- Timing controls
- Blocking vs. Non-blocking Proc. assignments
- Operators
- Programming statements
- Sensitivity lists
- Continuous assignments
- User defined tasks
- User defined functions
- File I/O
HDL Training PartnerThis course is developed and delivered by Willamette HDL. Founded in 1993, WHDL instructors are experts in Verilog, VHDL, SystemC and SystemVerilog.