SystemVerilog Open Verification Methodology (OVM)

Dauer: 3 Tage
Preis: 1.950 EUR
Partnummer:  231919

Description

This 3 day course is for engineers interested in developing SystemVerilog verification environments using the Open Verification Methodology (OVM).

First the student will learn Transaction Level Modeling (TLM) modeling and communication and  basic Testbench structure with various strategies for connecting to the DUT and analysis pieces such as scoreboards and coverage collectors.   Then the student will learn about writing reusable and flexible testbenches using the class factory, hierarchy, and configuration and managing test cases using scenarios and sequences.
The course is a consistent mix of lecture and lab-exercises.

You will learn how to

• Develop basic OOP based testbenches using TLM Interfaces and other OVM library base classes
• Develop testbenches with either TLM or RTL target devices
• Stimulus generation using constrained randomization
• Develop reusable and flexible testbenches
• Develop analysis components – scoreboards & coverage collectors
• Create reusable verification IP (VIP)
• Score boarding using functional coverage and other techniques
• Learn techniques for managing test cases

Throughout this course, extensive hands-on lab exercises provide you with practical experience using QuestaSim software and the OVM library.

Audience

Verification Engineers

Prerequisites

SystemVerilog for Verification training course or equivalent SystemVerilog experience

Key Topics

• Introduction to OVM
• Modeling Transactions
• Transaction-level Communication
  • TLM Interfaces
  • TLM Channels
  • Port & Exports
• Basic Testbench Structure    
  • Components
  • Threaded_component
  • Environment
  • Phases
• Introduction to the OVM Class Factory
• Connecting to the DUT
  • Transactors
  • Virtual Interfaces
  • Working with BFMs
• Generating Reports and Messaging
• Adding Analysis Components
  • Scoreboards
  • Coverage Collectors
  • Control Blocks
• Taking next steps: Writing Reusable and Flexible Testbenches
  • Hierarchy
  • Configuration
  • Factory Overrides
• Managing Test cases
  • Layered Stimulus (Scenarios)
  • Programmable Transaction Sequences
• Other OVM Classes
• Mixed Language Simulation
• Using SystemC TLM models in a SystemVerilog Test Environment