0-In Formal Verification
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Duration: 2 Tage
Pricing: 1480 EUR
Course Part Number: 234958
Course Overview
The 0-In Formal Verification course is for design and verification engineers interested in learning how to use formal verification techniques to improve verification quality. Assertion-Based Verification (ABV) is being used successfully in dynamic simulation to find and fix bugs faster. However, simulation methods have certain limitations that are easily addressed by Formal Verification. This class will introduce the student tofocuses on why, when and how Formal methods and how the application of fFormal vVerification techniques can be used to find formal proofs for critical design properties and find hotspot bugs that are and formal proofs not easily found withthrough simulation. . After completing the course Tthe student will be able to apply ABV methods with fFormal vVerification in the context of a wider assertion-based (ABV) verification tomethodology to find and fix tough bugs in their design that compliments their current simulation based verification flowusing an integrated methodology to what they are currently doing.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
You will learn how to
- Create and apply a verification methodology for Formal Verification.
- Apply Formal Verification to your design using 4 strategies.
- Write assertions for Formal Verification.
- Compile a Formal Model.
- Run Static Formal Verification.
- Interpret and Debug results from Static Formal Verification.
- Generate seed states from simulation.
- Run Dynamic Formal Verification.
- Apply advanced techniques when running Formal Verification.
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience in using 0-In Formal Verification software. Hands-on lab topics include:
- Application of Formal Methodology and Assertion Writing
- Compilation of the Formal Model
- Running and Debugging Static Formal Verification
- Running Seed Capture and Dynamic Formal Verification
- Advanced Topics such as initialization techniques and complexity reduction
Audience
- Verification Engineers
- ASIC and FPGA Design Engineers
Prerequisites
- Basic knowledge of ASIC/FPGA design and verification methods.
- Basic knowledge of Verilog and/or VHDL.
- Basic knowledge of an assertion language or library such as QVL, OVL, SVA, or PSL.
- Familiarity with the Questa simulator for HDL dynamic simulation.
Key Topics
- Introduction to Formal Concepts and Terminology
- Formal Verification Methodologies
- Best Practices for Writing Assertions for Formal Verification
- Compiling the Formal Model
- Running Static Formal Verification
- Debugging Formal Results
- Seed Capture and Running Dynamic Formal Verification
- Advanced Topics in Formal Verification