Calibre Rule Writing

Dauer: 4 Tage
Preis: 2.960 EUR
Partnummer: 058450

Description

Maximize your usage of Calibre, the industry standard for Deep Submicron Physical Verification. The "Calibre Rule Writing" course will teach you to effectively write and maintain Calibre nmDRC and LVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks.

The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors.

You will learn how to

• Write various types of DRC rules dealing with the width, spacing, overlap, enclosure, and extension requirements for different layers in your semiconductor process
• Write rules to control DRC output
• Use Boolean and topological operators to derive layers and use layer modifiers to change layer size
• Debug rule files
• Use edge directed checks to derive edge layers
• Use error directed checking to detect discrepancies
• Write a variety of complex, special, DRC rules dealing with antenna checks, line-end checks, direction of current flow checks, density checks, and metal fills specified in your process document, using state-of-the-art verification techniques
• Write rules to establish layout connectivity
• Write efficient rules that check the following: via checks, common metal checks, and contact DRC problems
• Write rules to control how cell data is used during DRC
• Deal with specific issues in hierarchical DRC
• Write rules to recognize different devices such as MOS transistors, resistors and capacitors of different types, bipolar transistors etc. in the layout
• Write rules to define your own custom devices.
• Extract various properties such as width, length, resistance and capacitance of these recognized devices, using the Built-in property language within Calibre LVS ^TM and compare values in the source netlist
• Write rules to extract layout connectivity
• Effectively utilize the text already present in the GDSII layout database, and to supplement it with text supplied through the rule file to annotate nets and ports
• Optimally use the various Calibre statements that deal with net and port names in the layout
• Write various LVS specification statements that control how the Layout Netlist extracted from the layout database is compared to the Source netlist
• Effectively block out selected cells during the LVS Netlist comparison process
• Write rules to control how cell data is used during LVS

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Calibre under the guidance of our expert instructors. Hands-on lab topics include:

• Preparing the Rule File and Running Calibre
• Displaying the Layout and Viewing Results
• Editing a Variable
• Using the Online Documentation
• Preparing the Layer Definitions
• Preparing the Layout Specification Statements
• Determining the DRC Output Control Statements
• Creating and Running the Rule File
• Improving the Output Display
• Write Internal RuleChecks
• Write External RuleChecks
• Write Enclosure RuleChecks
• Testing RuleCheck
• Designing Derived Layer Statements
• Testing Your Derived Layer Statements
• Writing Dimensional Checks using Derived Layers
• Writing Polygon-directed Rule Checks
• Designing Edge and Error-directed RuleChecks
• Testing Your Edge- and Error-directed RuleChecks
• Writing Connectivity Statements
• Writing RuleChecks to Test Connectivity of Metal1 and Metal2
• Writing RuleChecks to Test Metal1 Connectivity
• Designing and Testing a Poly Layer Antenna RuleCheck
• Designing Additional Antenna RuleChecks
• Layout vs. Layout
• Taking Advantage of Hierarchy
• Preparing the Layout Specification Statements
• Determining the LVS Output Control Statements
• Set the LVS Report options
• Report shorts and use LVS Isolate shorts
• Set Ground and Source names
• Improving the Output Display
• Designing Derived Layer Statements
• Testing Your Derived Layer Statements
• Writing Connectivity Statements
• Find Soft connects
• Create and name ports
• Place text objects into a layout design
• Write device recognition statements
• Use the COPY command to assist in troubleshooting/developing device statements
• Customize user-defined devices
• Writing Custom DEVICE statements
• Perform grid off checking
• Use the Built-in language to define device properties
• Use the Debugger to troubleshoot device statements

Audience

• Experienced IC Layout Engineers and Layout Verification specialists who will write, maintain, support, and optimize various DRC and LVS rule decks in their organization
• Experienced CAD Engineers and Managers who will be responsible for integration of the Calibre toolset in their design flow
• Experienced CAD specialists who interface with various foundries such as TSMC, UMC, Chartered, and integrate the rule decks supplied by these foundries into the verification flow
• Layout Verification specialists in foundries who are responsible for generating qualified rule decks in their various process offerings

Prerequisites

• Completion of the Calibre DRC/LVS class is very highly recommended
• Thorough knowledge of IC Layout techniques and procedures
• Experience with an IC layout editing tool
• Good Understanding of SPICE netlists
• Familiarity with UNIX
• Good understanding of layout verification concepts and experience with layout verification tools