Calibre xRC Parasitic Extraction

Dauer: 2 Tage
Preis: 1.480 EUR
Partnummer:  217011

Beschreibung

Post-layout simulation is both necessary and expensive. As process nodes shrink, the job of extracting the parasitics required for post-layout simulation is becoming both more critical and more difficult. In-house expertise and foundry-supplied PDKs are no longer the solution; they are the starting point. Performing extraction using Calibre xRC requires that you fully understand the many trade-offs you must make as well as the analysis needs presented by your designs. This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xRC tools and effectiveness.
 
Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. Upon completion of this course, students will understand the many trade-offs required to address the analysis needs presented by cutting edge designs and processes.

You will learn to

• Generate extracted netlists in six standard formats.
• Take advantage of the Calibre xRC 3-stage extraction process to generate multiple parasitic networks from a single extraction run.
• Leverage design hierarchy to obtain accurate results while keeping netlists manageable.
• Run Calibre xRC using the mode of your choice: GUI or batch.
• Review and interpret extraction results.
• Use advanced reduction techniques to minimize netlist size while maintaining a high level of accuracy.
• Customize foundry-supplied calibrated rules.
• Perform multi-corner extraction representing any or all of the process corners modeled by your foundry.
• Extract accurate parasitics in the presence of in-die variation or metal fill.
• Tailor your extraction runs to fit your design type (digital, memory, and analyog/RF and mixed signal) and process.

Hands-On Labs

Throughout this course, hands-on lab exercises provide you with practical experience using Calibre xRC under the guidance of our expert instructors. Topics include:

• Running Calibre xRC in either Batch or GUI mode.
• Interpreting transcripts and reports.
• Cross-probing parasitics in an open layout
• Exploring possible treatments for hierarchical designs, from flat to full hierarchical to hybrid.
• Generating extracted netlists in a variety of formats.
• Running simulations to compare pre-and post-layout netlists to reduced netlists.
• Working with a foundry-supplied PDK .
• Modifying PEX rules to avoid double counting of device parasitics.

Audience

This course is designed for:

• Layout Designers
• CAD Engineers
• Circuit Designers
• Silicon wafer fabrication teams needing to write, run circuit simulations, set-up or otherwise interpret Calibre xRC. This course should meet the needs of an audience of specialists who have knowledge of VLSI design. It is intended for users of xCalibre, Arcadia, StarRC, as well as, users who are new to parasitic extraction.

Prerequisites

• Calibre nmDRC/nmLVS training
• Basic knowledge of circuit simulation
• Ability to read circuit schematics
• Knowledge of layout verification concepts and tools

Key Topics

• Factors that Impact Extraction
• Types of Parasitic Networks
• Invoking Calibre xRC from the PEX GUI or Command Line
• Basic Extraction Work Flow Scenarios
• Factors that Impact Run Time
• Setting Up Calibre xRC for Best Performance
• Reading Reports and Transcripts
• Cross-Probing Hierarchical Parasitic Results
• Leveraging Hierarchy: Flat, Gate-Level, Full Hierarchical, and Hybrid Extractions
• Extracting Selected Nets
• Generating a Layout Based or Source Based Netlists
• Reduction Techniques
• Factory Recommended Reduction Strategies
• Reduction with Metal Fill
• Extraction Strategies for Memory Designs, Digital Designs, and Analog/RF Mixed-Signal Designs
• Working with Encrypted Rule Files
• Avoiding Double Counting of Capacitance
• Compensating for In-Die Variation
• Setting Up for Noise Analysis
• Setting Up for IR Drop Analysis