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Noida, India

Mentor NOIDA is located in an independent building in Logix Techno Park, a sprawling STP campus located in Sector 127 of NOIDA.

Noida, India


Mentor NOIDA is a Corporate R&D center of Mentor Graphics Corporation. The focus area for research and development in Noida is Scalable Functional Verification, advanced FPGA synthesis, Debug Tools with advanced Graphical User interface ?and HDL Language compilers for various EDA tools.

Scalable Functional Verification

Scalable Functional Verification is one of the key challenges faced by today's designers of complex System-On-Chip (SoC) applications. Traditional Verification techniques such as software simulation of RTL DUT with Verilog/VHDL testbenches is?no longer sufficient to meet the demands of a complex System-on-Chip Verification. Hardware acceleration is increasingly being used for finding bugs that take days and weeks of simulation. Also, there has been an explosion of Methodologies and Languages to improve Verification productivity. These methodologies include transaction-based modeling, assertion based verification, coverage driven Verification, constrained random Verification, Object oriented testbench modeling etc. Such methodologies can be adopted using Hardware Verification Languages such as System Verilog and SystemC which are both standards based languages.

The R&D team in Mentor Noida is actively working on developing tools and technologies in the Scalable Functional verification space. It is engaged in development of various aspects of Questa Verification Software (multi-language single kernel Verification platform offering simulation, assertion, formal and unified coverage collection tools) and in Hardware Acceleration solutions for RTL (compilers and run-time)

Mentor Noida is also pioneer in bringing the second and third generation of CoModeling technology (SCE-MI standards) for accelerating transaction level C testbenches. SCE-MI based testbench modeling allows testbenches to be written at a much higher level of abstraction where the untimed portion of the testbench can be written in C/VC++ and the timed?portion can be written in XRTL (an enhanced RTL subset) System Level Verification. Some patents have been applied in this area from Mentor NOIDA. Using the same SCEMI technology, higher performance simulation acceleration is achieved for traditional event-based simulations of HDL testbenches.

Advanced FPGA Synthesis Tools

Mentor Noida is actively involved in developing RTL synthesis and optimization technologies for FPGA devices. Every year, FPGA design starts are increasing and there is a large number of FPGA device families in the market. Most of the new FPGA devices come with a wide variety of complex embedded dedicated functional blocks, making the task of synthesis tool more complex.

Mentor NOIDA is actively working on advanced optimizations in RTL Synthesis including "technology-aware RTL synthesis" as well as? technology mapping to various FPGA families.

Graphical Debug and Language Front-End Technology

Another area where Mentor Noida is doing active development is in the area of Tcl/Tk based Graphical debug environments for various Mentor EDA tools. In addition, Mentor NOIDA is also instrumental in early adoption of SystemVerilog in many Mentor tools and replacement of older HDL front-ends with newer HDL front-ends that have been developed in NOIDA.

Mentor is actively looking for key software development professional in all the above areas for strengthening its R&D operation.
For more information on Mentor R&D opportunities, contact