Leonardo Spectrum: FPGA Synthesis
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Note: Training will be opened only with a minimum number of attendees
Duration
2 Days
Pricing
4000 ILS784 EUR
Description
Leonardo is used to transform a design from VHDL to a representation suitable for place and route. Techniques for area and timing optimization are presented.Objectives
- Transform register-transfer-level (RTL) VHDL into a structural design in an FPGA technology
- Describe the theory and tradeoffs inherent in design synthesis and optimization
- Optimize designs for area and performance
- Run the Xilinx and Altera place and route tools to create complete designs in both technologies
- Perform post-route backannotation simulations to verify correct functionality and performance
Audience
Designers with HDL-based design methodology experience.Prerequisites
Familiarity with supported workstation environments using the Sys V UNIX operating system, or Windows environments using either the Windows 98 or Windows NT operating systems, and basic text editors. In addition, students must have VHDL experience or have completed the Expert VHDL Verification course.Key Topics
- Introduction to Leonardo Spectrum
- Design Process Overview
- Synthesizing Your Design
- Optimizing Your Design for Area
- Optimizing Your Design for Performance
- Simulating Your Design
- Using Altera with Leonardo Spectrum
- Using Xilinx with Leonardo Spectrum
- Design Best Practices