0-In Assertion Synthesis

This course may be held at alternate loactions.  Search

Note: Training will be opened only with a minimum number of attendees

Duration

3 days

Pricing

Description

0-In Assertion Synthesis teaches you how to use Static and Dynamic (with Simulation) Verification Techniques to manage the convergence of your digital design verification process.  You will employ Libraries of Assertions along with basic Language constructs from PSL to instrument a design for functional coverage.  Various reports will be used to understand assertion density in the design and functional coverage (evaluations) during simulation.

You will learn how to

• Define basic assertions from a library
• Write PSL assertions for coverage
• Use 0-In Assertion synthesis to use assertions in  simulation
• Measure assertion density and functional coverage
• Understand the efficacy of your simulation regression suite

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Assertion Synthesis tools and methodologies.  Hands-on lab topics include:

• 0in_View Graphic User Interface
• Invoke and use basic assertion synthesis commands
• Run RTL Static check tools
• Create well instrument design assertions for Functional Coverage in Simulation
• Analyze assertion density
• Run simulation with assertions and analyze
• Define and utilize base PSL assertions.
• Understand the impact of various tests on the functional coverage of a design

Audience

Hardware, Software and System Engineers who perform VHDL, Verilog or mixed-VHDL/Verilog digital simulation and analysis.

Prerequisites

Some RTL VHDL or Verilog knowledge