Questa ADMS for A/MS Design Verification
- Add Courses
- Confirm Schedule
- Enter Contact Information
There are currently no dates scheduled for this class.
Course Part Number: 217225
Contact us for details about training at your site
Course Overview
This course will help you acquire the skills needed to maximize your usage of Questa® ADMS™ and realize its full impact on your analog/mixed signal designs. You will study design flows and representations, in particular top-down design and bottom-up verification and how Questa ADMS may be used to bring a design to completion. You will learn in detail — starting from the bases of the tools, compiling models written in any language, and running simulations — how to run effective mixed-signal simulations for both digital-centric and analog-centric flows. This will allow you to verify your full design with sensitive analog parts described at the transistor level.
Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.
You Will Learn How To
- Use Questa ADMS proficiently on large analog/mixed signal designs
- Compile text models written in VHDL, VHDL-AMS, Verilog and Verilog-AMS
- Set up, run, and interpret results
- Instantiate SPICE subcircuits in a HDL design (HDL on top methodology)
- Instanciate HDL models in a SPICE description (SPICE on top methodology)
- Appropriately insert and configure boundary converters between analog and digital parts of your design
- Run full chip verification with ADMS ADiT™
- Make effective use of advanced features and tips specific to your design methodology
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa ADMS software. Hands-on lab topics include:
- Introduction to Questa ADMS
- Managing Libraries
- Running Simulations
- Using EZware
- HDL Instantiating SPICE Designs
- SPICE Design Configuration
- Boundary Models
Prerequisites
- Knowledge of principals of SPICE simulation
- Working knowledge of Hardware Description Languages (VHDL and/or Verilog)
- Familiarity with Questa® is a plus
- Practical experience with analog design and simulation is a plus