Visual Elite

HDL設計環境 Visual Elite を使用するためのデザイン・エントリからデータ 管理、シミュレーション、Visual Elite独自のデバッグ環境といった基本的な 操作方法について学びます。  

価格　\52,500（消費税込）
期間　1日間
対象　回路設計者、システム設計者
前提知識　VHDL、Verilog の言語知識を有する方。 

コース内容 

• Visual Elite の概要  
• 設計フローとデータ管理  
• Visual Elite のエディタと基本操作
  
  
  • ブロックダイアグラム  
  • ステートダイアグラム  
  • フローチャート  
  • 真理値表
   
• テストベンチ  
• 設計資産の読み込み  
• HDL 生成  
• VHDL内蔵シミュレータ、もしくはModelSim によるシミュレーション  
• Visual Elite独自のデバッグ機能  

※実習はWindows 版にて行います。  

※お問い合わせもしくは受講予約時に、ご使用の言語（VHDL/Verilog）をお申し出いただけますと幸いです。

Duration: 1 Day
Price:  52,500 JPY including tax
Course Part number: 232834

Description

The Visual Elite course was developed to help you understand the graphical design entry for HDL, the design management, simulation & debug.

Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

You will learn how to

• The Visual Elite overview
• The graphical entry benefit
• How to entry graphical design of block diagram, state diagram, flowchart, truth table
• How to entry HDL for text based.
• How to control of design management
• How to write design document
• How to create stimulus for simulation
• How to simulation and debug
• How to re-use legacy design
• How to generate HDL from graphical entry
• How to translate from the HDL text to the graphical design

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Visual Elite software. Hands-on lab topics include:

• Create new library
• Create new graphical design of block diagram, state diagram, flowchart, truth table
• Create stimulus
• Simulation your design
• Generate HDL from your design
• Import legacy HDL design
• Translate from the HDL text to the graphical design

Audience

• FPGA and ASIC Designers
• CAD Engineers and Managers who will be responsible for integrating HDL Designer Series into their design flow
• Members of CAD support groups who are responsible for increased productivity of FPGA and ASIC design teams

Prerequisites

• Basic knowledge of FPGA and ASIC and design techniques and procedures
• Reading knowledge of HDL languages (VHDL or Verilog)
• Familiarity with Windows NT, 2000, XP or Solaris and Redhat Linux operating systems 

Key Topics

• How to use Visual Elite
• The specification of lab design
• Start Visual Elite
• Open library browser
• Create new library
• The editor common operation
• Entry the block diagram
• Entry the state diagram
• Entry the flowchart
• Entry truth table
• Create the stimulus for simulation
• Design check
• Simulation and debug
• Generate HDL
• Import HDL
• Translate the HDL text to graphical design