System Modeling with TLM and Vista Architect

Course Part Number: 248999

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Course Overview

The System Modeling with TLM and Vista™ Architect course will help you become familiar with the capabilities of Vista for TLM architectural analysis by investigating architectural models and making trade-offs between the models. Platform creation, modeling techniques, and debug and analysis are just some of the topics of Electronic System Level (ESL) design that will be covered.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.

You Will Learn How To

• Understand the overall goals and objectives targeted in system modeling and virtual prototypes
• Model a simple peripheral: configuration, integration
• Produce efficient models in SystemC
  • Event versus clock-based models
  • How to model hardware functions in a programming language
  • How to model concurrency
• Model timing
  • Types
  • Latency
  • LT/AT synchronization
• Analyze the platform
  • For performance
  • For power
• Understand the HW/SW co-simulation aspects
  • What is a processor model in Vista?
  • What are the differences between the virtual model and the real/actual model?
  • What are the implications of moving a function between HW and SW?

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Vista software. Hands-on lab topics include:

• Model architecture for multi-core ARM, one microprocessor for Linux OS execution, one mircroprocessor for native code execution, all including AXI, UART, FLASH, Memory, and Generic IO
• Labs will
  • Explore capabilities of working design
  • Running simulation, stepping through SW and HW models
  • Architecture debug
  • Performance investigation
  • Exploring modeling style and its affects on execution
  • Analyzing and adjusting platform to meet timing and performance requirements
  • Produce new model component and peripherals for AXI bus
  • Model interrupts and use pre-packaged interrupt handler
  • Understand concurrency and ability to do architectural trade-off analysis
  • Adjust code execution
  • Integrate realistic traffic flows

Prerequisites

Familiarity with concepts of

• Computer and system architecture
• Hardware simulation languages and modeling
• Programming in C; SystemC knowledge helpful and encouraged, but not required
• Verilog/VHDL RTL coding and simulation/modeling knowledge also helpful
• Basic understanding of SW debuggers, breakpoints, and step-wise execution helpful

Key Topics