ModelSim: HDL Simulation

Duration: 1 Day
Pricing: 52,500 JPY including tax
Part number: 202339

Description

HDLシミュレータであるModelSimを使用するためのコンパイルからシミュレーションといった基本的な操作方法について学びます。

 価格　\50,000（消費税込
 期間　1日間
 対象　回路設計者、システム設計者
 前提知識　VHDL, Verilogいずれかの基本的な言語知識を有する方。 

コース内容

• ModelSimの概要
• ModelSimの基本操作
• プロジェクト機能
• ModelSimウィンドウ
• デバッグ環境
• 各コマンドについて
• バッチ・シミュレーション
• VHDL、Verilog混在モデルの作成方法
• その他の機能

※お問い合わせもしくは受講予約時に、UNIX 版／Windows 版の希望もお申し出いただけますと幸いです。

HDL Simulation with ModelSim teaches you to effectively use ModelSim to verify VHDL, Verilog, and mixed VHDL/Verilog designs. You will learn how ModelSim supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

You will learn how to

• Invoke the ModelSim program
• Prepare VHDL and Verilog data for use by ModelSim
• Create and use design Libraries
• Use ModelSim commands to run a simulation
• Create a simple simulation script
• Use ModelSim for batch simulations
• Use the ModelSim Graphical User Interface
• Create a ModelSim project
• Simulate VHDL or Verilog designs
• Simulate mixed VHDL/Verilog designs

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using ModelSim.  Hands-on lab topics include:

• ModelSim Graphic User Interface
• Invoke and use basic simulation commands
• Create a basic simulation script
• Create data libraries and simulate VHDL and Verilog designs
• Detect Verilog hazards
• Create a VHDL project
• Detect and fix an error in a VHDL design
• Create and simulate a mixed VHDL/Verilog design

Audience

Hardware, Software and System Engineers who perform VHDL, Verilog or mixed-VHDL/Verilog simulation and analysis.

Prerequisites

• Some VHDL or Verilog knowledge
• Some familiarity with digital design concepts 

Key Topics

• ModelSim Windows
• Steps to Invoke a Design
• Libraries in the ModelSim Environment
• Supporting Files
• VHDL/Verilog Design Methods
• Create and simulate mixed VHDL/Verilog HDL designs
• VHDL Configuration files
• VITAL Simulation Modeling language
• Design Hierarchy / Building and Simulating Designs
• Verilog Hazards