Calibre nmDRC/LVS

Duration: 2 Days
Pricing: 105,000 JPY
Part number: 063568

Description

IC レイアウト検証ツール Calibreを使用して、ルールファイルの作成方法、DRC/LVSの実行方法について学びます。

価格　￥100,000（消費税込）
 期間　2日間
 対象　IC設計者
 前提知識　マスクパターンに関する知識をお持ちの方

コース内容

• ルール・ファイルの設定

• DRCルールの記述方法

• LVSルールの記述方法

• デザイン・ルール・チェック

• 回路図とレイアウト図の比較検証

Calibre is the industry standard for Deep Submicron Physical Verification. Realize its full impact on your design process by attending the Education Services "Calibre nmDRC/LVS" course. It will teach you to effectively use Mentor Graphics Calibre software in your layout verification flow and will empower you to analyze the Calibre nmDRC and Calibre LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset.
 
Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. 

You will learn how to

• Use Calibre nmDRC and Calibre LVS proficiently in the flat and hierarchical modes
• Debug the flat and hierarchical DRC and LVS results using Calibre RVE^TM (Results Viewing Environment) and a layout editor
• Interpret the various specification statements in your rulefile dealing with layout and source input, nmDRC and LVS results databases and reports, layer definitions, derived layers, DRC rulechecks, LVS device recognition statements, CONNECT statements
• Interpret simple DRC checks such as width, spacing, enclosure checks
• Interpret complex, state-of-the-art DRC checks such as antenna checks, current flow checks
• Do netlist vs netlist and layout vs layout (LVL) comparisons
• Identify and locate the following DRC-related problems: external spacing of edges on different or same layers; internal spacing of edges on different or same layers; measurement of geometry on one layer enclosed by geometry on another
• Identify and locate the following LVS-related problems: shorts and opens, including those on power and/or ground nets; floating or isolated nets; pin swapping; device problems; soft-connections; and texting (naming) problems
• Interface Calibre to tools from other vendors

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Calibre under the guidance of our expert instructors. Hands-on lab topics include:

• Rulefile setup
• Flat and Hierarchical DRC execution
• DRC results debugging in a layout editor, using Calibre RVE
• Flat and Hierarchical LVS execution
• LVS Shorts and Opens
• LVS Power-Ground Shorts
• LVS Device mismatches
• Soft-Connection checking
• LVS Texting errors

Audience

• IC Layout Engineers and Layout Verification specialists who will use Calibre nmDRC and Calibre LVS tools for layout verification.
• Front-end Design engineers who would like to have a better understanding of the back-end verification flow.

Prerequisites

• Knowledge of IC Layout techniques and procedures
• Experience with an IC layout editing tool
• Understanding of SPICE netlists
• Familiarity with UNIX
• Knowledge of layout verification concepts and tools (helpful but not required)

Key Topics

• IC Layout Verification Overview
• Introduction to the Calibre toolset
• DRC concepts and basic DRC checks
• Complex DRC checks
• DRC examples and Debugging
• Hierarchical DRC
• Overview of Flat and Hierarchical LVS
• LVS Shorts and Opens
• Power Ground Short Isolation
• Device Recognition and Connectivity Extraction
• LVS Texting