Design Architect-IC A/MS Simulation Environment

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Duration: 2 Days
Pricing: 105,000 JPY including tax
Course Part Number: 210270

Contact us for details about training at your site 

Course Overview

Design Architect-IC Analog & Mixed Signal Simulation Environment will teach you to capitalize on the extensive capabilities of Design Architect-IC to effectively and efficiently design and simulate analog and mixed-signal IC designs. The emphasis of the course is on analog design. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with tool usage experience under the guidance of our industry expert instructors. You will be presented with real world analog design challenges and the tools to simulate and analyze designs and resolve these challenges in a methodical manner. 

You will learn how to

• Take advantage of the Design Architect-IC simulation flow
• Quickly build hierarchical blocks using a top-down or bottom-up design methodology
• Model conditional and repetitive circuitry using advanced data modeling features
• Use shortcuts like On-line help, command line functions and a range of palettes, pop-up menus, function keys, hot keys, and stroke functions needed to rapidly create designs
• Do simulation setup and netlisting for analog and mixed-signal simulation
• Use the Eldo kernel to quickly perform advanced analog simulations and parametric sweeps
• Use ADVance MS^TM  (ADMS) to perform simulations using schematic and VHDL-AMS based components
• Use the Xelga waveform viewer to view results

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Design Architect-IC software. Hands-on lab topics include:

• Schematic and symbol entry and generating a SPICE netlist
• Model a four-bit adder using function blocks data type
• Setup hierarchical simulation test benches
• Time domain analysis, accuracy and measurements, parameterized design
• Noise analysis
• Simulation of a 6th order SC BP filter design and FFT analysis
• Monte Carlo simulation using a 4th order Butterworth Filter
• Simulation of a 6th order BP SC filter with ADMS

Audience

• IC Layout Engineers and Layout Verification specialists who will use Calibre DRC and LVS tools and the Virtuoso Layout Editor for layout verification
• Front-end Design engineers who would like to have a better understanding of the back-end verification flow
• Front-end Design engineers who would like to have a good understanding of the back-end verification flow

Prerequisites

• Familiarity with concepts of IC layout techniques and procedures.
• Understanding of SPICE netlists and models.
• Knowledge of analog andmixed signal circuit design.
• Knowledge of text modeling languages such as VHDL, VHDL-AMS, Verilog, and Verilog-AMS.
• Familiarity with Windows 98, NT, 2000, XP ,Linux, or UNIX operating systems

Key Topics

• Quick Start and the Falcon Framework
• Design Flow and Editors
• Analog Simulation
• Mixed Signal Simulation
• Advanced Data Modeling Features