DxDesigner for Expedition PCB Flow (v2007)

Duration:  3 Days
Pricing: 154500 YEN
Course Part Number: 236553

Contact us for details about training at your site

Course Overview

The DxDesigner for the Expedition Flow course was developed to improve your knowledge and skills with Design Definition solutions. Using the DxDesigner tools suite, you will gain proficiency in project management with Dashboard, schematic capture with DxDesigner, part selection using DxDatabook and much more. You will also learn how to prepare your final schematic for interfacing with Mentor’s Expedition PCB layout tool.

Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors. 

You will learn how to

• Use DxDesigner proficiently in the creation of flat and hierarchical schematic designs
• Place wires and buses in the design to create net connections
• Use DxDatabook to search, select, and verify parts used in your design 
• Create symbols for your schematics through a variety of methods, including the Symbol Wizard
• Effectively build intelligence into your design using properties
• Compile, package and export your schematic to Expedition PCB for place and route
• Use CES to create and assign constraints to your design and pass that information to Expedition

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using DxDesigner software. Hands-on lab topics include:

• Creating a project and setting up projects in Dashboard and DxDesigner
• Configuring DxDesigner
• Schematic creation for flat and hierarchical designs
• Symbol graphics creation
• Adding Properties to symbols and schematics
• Design Reuse
•  Net label cross-referencing 
• Interfacing to Expedition PCB layout tool
• Setting constraints with CES
•  A student design challenge that pulls together all aspects of the tool discussed during class

Audience

• Engineers and schematic designers who will use DxDesigner to create schematics that will be used as "front end" designs for Mentor’s Expedition PCB layout tool
• CAD Engineers and Managers who will be responsible for integration of the DxDesigner tool suite in their design flow
• PCB Designers who would like to have a good understanding of the front-end schematic capture process

Prerequisites

• Familiarity with Windows XP, NT, 2000 or UNIX operating systems.

Key Topics

DxDesigner Introduction

• General Design Flow
• DxDesigner to Expedition PCB Flow
• DxDesigner Environment
• Tools Overview
• Dashboard
• Library Manager
• DxDesigner
• CES
• Espedition
• Accessing Help
• InfoHub
• SupportNet
• Lab Exercises

Project Set Up

• Creating a New Project
• Defining Project Settings Information
• Project Files
• Supporting FIles
• The WDIR
• Project Templates
• Save, Backup, and Rollbakc
• Lab Exercises

Schematic Design

• Operating an Existing Project and Schematic
• Adding Schematics to a Design
• Navigating: Panning and Zooming
• Selection Techniques
• Selection Filter
• Placing Components
• Adding Components Using DxDataBook
• Adding Net Connections
• Naming Nets
• Find and Replace
• Arrays
• Lab Exercise

Connectivity            

• Adding Busses
• Bus Names
• Naming Buses
• Ripping Buses
• Bus Contents
• Defining Global Signals
• Using Ports
• Lab Exercise

Hierarchical Design

• Hierarchical Blocks
• Top-Down Process
• Symbols
• Bottom-Up Process
• Navigator
• Changing the Root Schematic
• Lab Exercise

Design Reuse

• Same Sheet Copy and Paste
• Copy From Other Projects
• Hierarchal Symbols versus Reuse Blocks
• Using Reuse Blocks
• Lab Exercise

Verification       

• DxDataBook Verification Methods
• DxDataBook Live Verification
• Design Rule Checking
• Lab Exercise

Forward to Layout

• Using Packager
• DxDesigner to Expedition: Forward Annotation
• Expedition to DxDesigner: Back Annotation
• Lab Exercise

CES

• CES in the Design Flow
• Invoking CES in DxDesigner
• What Is a Net Class?
• Trace Properties
• Via Assignments
• Clearance Rules
• Setting Up Class to Class Clearances
• Creating a Constraint Class
• Creating Diff Pairs
• Setting Up Differential Pair Constraints
• Signal Integrity Constraints: Parallelism and Crosstalk Rules
• Lab Exercise

Schematic Documentation

• PartsLister
• Cross Referencing
• PDF Schematics
• Printing
• Archiving
• Lab Exercise

Review of the Course Topics

• Review
• Challenge Lab Exercises