Duration: 1 day
Pricing: 200 USD
Course Part Number: 202339

Course Overview

HDL Simulation with ModelSim teaches you to effectively use ModelSim to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

YOU WILL LEARN HOW TO

• Invoke the ModelSim program
• Prepare VHDL and Verilog data for use by ModelSim
• Create and use design Libraries
• Use ModelSim commands to run a simulation
• Create a simple simulation script
• Use ModelSim for batch simulations
• Use the ModelSim Graphical User Interface
• Create a ModelSim project
• Simulate VHDL or Verilog designs
• Simulate mixed VHDL/Verilog designs

HANDS-ON LABS

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using ModelSim. Hands-on lab topics include:

• ModelSim Graphic User Interface
• Invoke and use basic simulation commands
• Create a basic simulation script
• Create data libraries and simulate VHDL and Verilog designs
• Detect Verilog hazards
• Create a VHDL project
• Detect and fix an error in a VHDL design
• Create and simulate a mixed VHDL/Verilog design

AUDIENCE

Hardware, Software and System Engineers who perform VHDL, Verilog or mixed-VHDL/Verilog simulation and analysis.

PREREQUISITES

• Some VHDL or Verilog knowledge
• Some familiarity with digital design concepts

KEY TOPICS

• ModelSim® Windows
• Shell Commands
• Steps to Invoke a Design Using ModelSim Commands
• Steps to Invoke a Design Using the GUI
• The Advantages of Using Projects
• Libraries in the ModelSim Environment
• Create and simulate mixed VHDL/Verilog HDL designs
• Design Hierarchy / Building and Simulating Designs
• Verilog Hazards

Related Courses

• ModelSim Advanced Topics
• 0-In Assertion Synthesis
• SystemVerilog for Verification
• Verilog Fundamentals for SystemVerilog
• Eldo Simulation