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Seminars

Quick Links: ASIC & FPGA | Verification

ASIC & FPGA

Workshop: ASIC Prototyping – Easing the Transition from ASIC to FPGA Design
Very large and complex FPGAs introduced new opportunities for prototyping ASIC designs. With the increased capacity and performance that is now available in current FPGA offerings, ASIC systems can easily be verified and tested before costly decisions are made about the final design. The transition for ASIC design to FPGA design, however, is not always a push button affair. Considerations must be made for design content and the differences between the ASIC technology and the FPGA device. Choosing a design flow that will both accommodate the existing ASIC design and provide enough feedback and analysis capabilities in the prototyping process is instrumental in providing value from ASIC verification. This workshop will introduce:

  • ASIC prototyping with FPGAs
  • Design considerations that must be made in both the ASIC and the FPGA design to facilitate both devices
  • Design debugging and analysis
  • Performance enhancement techniques to provide the most realistic verification platform.


Workshop: 7 Habits of Successful FPGA Design
Can you design Virtex-5, Stratix® III and today's other high performance FPGAs in a predictable manner that gets your company's products to market on time? Without good habits to help you create correct, portable designs and tools that enable you to reach your design and project budgets, you could jeopardize your company's business objectives. This workshop will teach you 7 habits that will make it possible for you to design FPGAs to meet all of your FPGA design goals while using Mentor Graphics' Precision® Synthesis. Precision is optimized for all complex FPGA architectures and utilizes sophisticated RTL and physical optimization algorithms to minimize the number of design spins needed to obtain your final complete design.

  • Use Standard Languages & Constraints for Design Portability
  • Design for FPGA Device Selection Freedom
  • Iterate to Debug Constraints
  • Apply Comprehensive Design Constraints
  • Use Advanced Timing Analysis to Address Timing Issues
  • Exercise Superior Optimization
  • Minimize the Impact of Design Changes

Workshop: SystemVerilog for FPGA Designers
Modern FPGAs have seen tremendous advances in both performance and capacity. With these increased capabilities, designers are faced with the daunting task of verifying and validating that their design intent is represented in the finished product. SystemVerilog provides a comprehensive language that is a natural extension of Verilog, with the benefits of providing constructs with clearer intent, enumerated types, integrated assertions for simulation and higher language constructs which support design hierarchy and Object Orientated Programming (OOP) styles.

Mentor Graphics’ Precision® Synthesis provides the most complete SystemVerilog coverage of this language in FPGA synthesis. This easy-to-use tool empowers designers to utilize sophisticated RTL and physical optimization algorithms to clearly express their design intent.

  • Introduction to effective design with SystemVerilog
  • Learn how to write fewer lines of code that actually do more
  • Best practices for avoiding race conditions (Includes “8 Guidelines to Avoiding Verilog Race Conditions” from http://www.sunburst-design.com/)
  • Mixing Verilog, VHDL and SystemVerilog in the same design

Workshop: RTL Reuse Workshop
This workshop will show you a practical methodology to reuse RTL. Whether you inherit code from a legacy design or an outsource design group, reuse is a fact of life in modern design. Learn how to maximize your time and effort to determine code quality for reuse. Designs are often completed and left with little or no documentation. Having a practical RTL reuse methodology coupled with a simple web based repository can be implemented with minimal effort and provide ongoing visibility to RTL available for reuse in your company.

In this workshop you will learn a practical methodology to reuse RTL and learn more about the simple repository.

  • Automatically analyze code composition and dependencies
  • Quickly comprehend the design structure and hierarchy
  • Leverage leading standards to check code for common problems
  • Assess quality of the code
  • Visualize RTL to understand its structure and behavior
  • Automate documentation


Workshop: IO Designer Overview
The trend towards ever-larger FPGAs shows no sign of slowing down, with some devices now offering more than 1500 user-definable I/O pins. Taking advantage of all of those pins and getting the maximum system benefit afforded by FPGAs, with their unique ability to swap pins, can be a time-consuming, error-prone and costly task. These new devices require a tool that automates the process of connecting pins to the PCB and brings the FPGA and PCB design teams together in a common environment allowing them to quickly see the ramifications of their decisions on the overall system.

An effective design process requires:

  • A bridge between your existing FPGA and PCB design flow
  • Consistency between the HDL, FPGA and PCB environments
  • Automated detection of changes in HDL, FPGA and PCB related files
  • Automated flow to eliminated error prone manual tasks
  • Assist with defining optimal I/O assignments for both the FPGA and the PCB

We are offering you a workshop that will take you through a typical design process with the growing demand of FPGA and PCB design and a fast and efficient solution for assigning the I/O of your FPGA to device pins. This workshop will provide an overview of IO Designer technology.

You will learn how to:

  • Setup IO Designer and configure it to meet your standard
  • Do intelligent IO assignment and early PCB design
  • Generate PCB data
  • Optimize pin assignment with the consideration of PCB system

Who Should Attend:

  • Design engineers doing FPGA and/or PCB design
  • Engineering and project managers

Time: 9:00 - 3:00


Workshop: FPGA Re-spins are No Longer "Free"
Modern FPGAs present huge opportunities and are opening new markets for FPGAs, but their high performance and high densities are throwing the traditional "design-burn-and-test" process out the window. Re-spinning the design in response to a specification violation found in the lab is no longer quick and easy, but rather painful and very costly. This workshop will demonstrate effectively how to meet complex design requirements by analyzing performance and verifying functionality early and frequently throughout the design process, where the overall pain and cost for fixing errors is much less. Presentation and hands-on exercises will exhibit:

  • how coding style rule checking can be used prior to simulation to catch defects and flag potential defects
  • how introducing assertions into verification can complement HDL testbenches by describing the design's expected behavior
  • how the right combination of RTL and physical synthesis techniques will help ensure success in meeting timing and area constraints
  • how cross-probing between physical, gate-level, and RTL representations of the FPGA design provides full visibility, facilitating the initiation of appropriate actions to correct problems before reaching hardware
  • how to minimize the impact of Engineering Change Orders (ECOs).

Finally, we will address how to identify pin assignment early on by synchronizing the HDL with the board design. This result in a reduction of PCB re-spins as well as FPGA re-spins.

Target Audience: FPGA designers and team/project leaders targeting the more recent FPGA architectures from Actel, Altera, Atmel, Lattice Semiconductor, and Xilinx

Duration: 6-hour workshop, 30% presentatation/70% hands-on

Mentor Graphics Products Used: HDL Designer, ModelSim/Questa, Precision Synthesis, I/O DesignerLunch and Learn: Reduce your HDL Design Cycle up to 30%


Lunch and Learn: Reduce your HDL Design Cycle up to 30%
Overview
The challenge for designers today is to meet deadlines. Maximizing your productivity to remain competitive in the global market is a must. Time savings can be gained through improving techniques and having the right tools to automate many of the tasks that would otherwise consume hours and even weeks to complete.
An effective design process involves:

  • Creating a design or using existing IP
  • Understanding the hierarchy and interconnects
  • Checking the quality of the code
  • Documenting for review and future use

To learn how you can save time and improve the quality of your design, Mentor Graphics cordially invites you to attend a FREE "Lunch & Learn" seminar.

A complimentary lunch will be provided during the event. Seating is limited, so register now to reserve your space.

Who Should Attend

  • Design engineers doing digital IC design
  • Engineering and project managers

What You Will Learn
This session will take you through a typical design process and highlight areas where trade-offs are often made. This seminar will provide an overview:

  • How to create an instant design environment
  • Roundtrip integration with simulation/synthesis to reduce iteration time
  • Quickly create documentation
  • Simplify IP design reuse

Lunch and Learn: Achieving Timing Closure in FPGAs with Precision Synthesis
FPGAs have made amazing advances in performance and capacity, but with higher performance and multi-million gate designs, timing closure is becoming exponentially more difficult. What are needed are flows derived from the ASIC world, but optimized for today's most complex FPGA architectures. This hands-on workshop will use Precision Synthesis technology with advanced RTL and Physical optimization algorithms to show you how to use capabilities such as technology specific mapping, register re-timing, logic replication, logic restructuring, placement optimization, and re-synthesis in a fully interactive environment to achieve the most out of your FPGA design.


Lunch and Learn: ModelSim 6.3 Seminar
ModelSim continues to evolve as the new Standard Design and Verification languages are supported. Native support of Standard languages like SystemVerilog and SystemC add significant new functionality to the Simulation kernel and User interface. ModelSim 6.1 delivers across the board with SystemVerilog for design support for more concise design descriptions to DPI capabilities and GUI enhancements that improve the analysis and debug of designs.

This presentation will introduce the new features that are available to ModelSim users.


Lunch and Learn: Accelerating RTL Reuse
Take more time than a seminar affords to provide your customers with a practical approach to RTL reuse in their design flow.

  • Automatically analyze code composition and dependencies
  • Quickly comprehend the design structure and hierarchy
  • Use new techniques to ensure interface compliance
  • Leverage leading standards like RMM (Reuse Methodology Manual) to check code for common reuse mistakes & problems
  • Check the quality of unfamiliar RTL and catch bugs before you simulate
  • Visualize RTL to understand its structure and behavior
  • Automate documentation of new code.

Lunch and Learn: IO Designer
This seminar is geared toward companies that have multiple designers and engineers (FPGA, Schematic, PCB, and High-Speed) collaborating on a project.

Although each designer has well-established working processes within their own domain, communication between design areas can be troublesome from a project-management perspective, as the overall process is slow and full of manual, error-prone steps.
Attend this L&L if your design team encounters problems like these:

  • FPGA Designer: Is forced to reduce the flexibility that could account for PCB routability and high-speed issues in proper I/O design due to the need to lock pin assignments early in the process. Has to pass data manually to the schematic designer. Must constantly hand-verify FPGA and/or schematic data to ensure that no errors occur when changes are made.
  • Schematic Engineer: Has to create symbol fractures by hand. Concerned that the fractures don't correlate to the logical connections within the FPGA code.
  • PCB Designer: Wants to fix timing and route complexity issues by swapping pins, but is locked out of the design. Requires a method for verifying that proposed pin swaps are legal. Needs to go all the way back to the FPGA Designer to change the FPGA I/O to accommodate board rerouting requests.
  • Project Manager: Must manage a single project across isolated processes and teams. Has a talented team, but has difficulty coordinating communications and data transfer between team members. Loses time and money over board respins caused by inter-team errors in data synchronization (such as to pin assignments, signal types or the transfer of FPGA symbols to the board).
    You'll learn an effective methodology for reducing board spins and resolving the issues described above. Send your entire team to learn how complex FPGAs and PCBs can be designed by redefining your current solution.

Who Should Attend?

  • Teams of FPGA and PCB designers and engineers
  • Project managers responsible for delivery of end products

Duration: 2 hours


Verification


TechTalk (Presentation + hands on): Adopting SystemVerilog Assertions
The SystemVerilog language enables several new verification methodologies which target increased verification productivity. Assertion Based Verification, or ABV, is a powerful methodology which increases verification productivity through improved bug detection/isolation as well as shortening the time required to debug design failures. Coverage Driven Verification, or CDV, increases verification productivity by providing true functional coverage metrics which can easily detect and report the occurrence of important test sequences and design corner-cases. This seminar is designed help design and verification engineers adopt ABV for VHDL or Verilog designs by using a hands-on approach to learning. The seminar provides examples of both assertions and functional coverage points. The labs give the attendee the opportunity to incorporate assertions and functional coverage points on a reference design. The reference design examples are VHDL and Verilog.

Attendees should have a working understanding of Verilog or VHDL. Some knowledge of Assertions is a plus.


TechTalk (Presentation + hands on): SystemVerilog Testbench Components for VHDL
The SystemVerilog language enables many new verification methodologies that target increased verification productivity. This technical seminar focuses on how to best implement re-usable verification components like generators, drives, monitors and scoreboards for VHDL designs. Constrained-randomization and functional coverage are also covered. This "hands-on" seminar will show how-to implement an efficient transaction based verification environment purely in SystemVerilog.

The target audience is verification engineers or designers that like to learn and understand how to implement a transaction based verification environment using SystemVerilog. The attendee should understand VHDL and Verilog.


TechTalk (Presentation + hands on): SystemVerilog Constrained-random Verification Seminar
In the current verification environment engineers write directed tests to verify the functionality of their design. Once functionality has been verified they add more tests to the suite. Quite often this process is time consuming and many corner cases are missed.

Rather than require the verification engineer to write tests to check each feature individually, constrained-random verification (CRV) effectively allows a single test to check multiple features. With this methodology, each "test" can check many possible scenarios, and the simulator itself chooses a specific scenario for each invocation. This can be an extraordinarily powerful verification methodology, but it is one that is not supported well by either standard Verilog or VHDL.

SystemVerilog has been designed specifically to support this methodology. This seminar will provide basics for users to start efficiently generating constrained-random stimulus with SystemVerilog


Lunch and Learn: PSL Assertion Based Verification
Description: PSL What Is It, And How To Leverage It Today. The PSL Assertion Language is an evolutionary step to aid in verifying today's complex designs. This technology has already been embraced by some of the leading technology firms around the world. This seminar is an introduction to what PSL is with examples of how to use it in your Verification environment today. Discover not only the benefits of Assertion Based Verification for increased error detection/isolation and debug productivity, but also how it can be used to create a Coverage Driven Verification methodology. The concept of a Coverage Driven Verification Methodology incorporates the Functional Coverage capabilities and a feedback mechanism of this Functional Coverage information to the testbench. Providing the Functional Coverage information back to the testbench, allows it to dynamically alter its input stimulus to target those Functional Coverage points that have not been exercised. Come see these new PSL features in Questa.

This seminar is targeted to design and verification engineers/managers who are doing a RTL level functional verification for VHDL or Verilog based ASIC or FPGA designs.