With the Design For Test capability in Valor MSS Process Preparation, read details and see a video by clicking on the following link, we can analyze a board and determine the amount of physical test access to it.
However the question of how to compare test coverage across multiple boards comes up from customers I talk with. In simple terms, the requirement is for at least one probe per net but that is a measure of test access and not testability. I am interested to hear from the test engineers out there how they calculate test coverage across a board or at the component level to know where escapes could happen and hence be able to address them.
There are a number of methods around such as the Agilent developed techique of PCOLA/SOQ or the simpler model of the International Test Conference MPS. Do you use these or just calculate coverage based on number of nets probed or number of pins covered for each component?
I am interested to hear your feedback.