Test Engineers are typically given the requirement to get 100% of nets probed at electrical test with the thinking that this delivers 100% testability. Unfortunately 100% accessibility is not the same as 100% testability. There are a number of reasons why this is not the case but here is a easy one. Typical boards contain integrated circuit (IC) components and power supplies. These power supplies usually have large polarized capacitors across the power rails to smooth the supply but also small capacitors close to each IC to remove high frequencies that may harm the ICs. The large capacitors may be 100uF whereas the small bypass capacitors are 100nF. Say we have 10 of these small capacitors then these will total 1uF of capacitance along with the large capacitor and we have a total of 101uF which is well within the tolerance of the larger capacitor (typically at least 20%). As it is usual to get probes placed on the power rails these 10 bypass capacitors will be probed but not testable due to the large capacitor in parallel with them. In other words 100% accessible does not equal 100% testable.
In Valor MSS Process Preparation, the Design For Test (DFT) analysis considers this scenario in conjunction with Defects Per Million Opportunities (DPMO) to know if the component can be tested or not. If it can’t the DPMO of the part will contribute to the overall DPMO of the board. If it is fully testable then the DPMO will not contribute to the overall DPMO of the board. The using a simple equation, yield can be predicted based on the Defects Per Board. In our analysis it is common to see a theoretical yield of less than 100% which is based on 100% of nets being accessed due to these types of circuit configuration.
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