Sign In
Forgot Password?
Sign In | | Create Account

To DFT or not DFT? That is not a question

Mark Laing

Mark Laing

Posted Sep 24, 2011
0 Comments

Another area I discussed in my recent article for PCB007 was with Design For Test or DFT. Ensuring that accurate test or inspection techniques have been catered for before a layout is signed off will ensure that any assembly or component issues will be found as early as possible in the manufacturing process. For each additional step during the manufacturing process it is estimated that the cost of corrective action increases by a factor of 10. Therefore early detection of issues can significantly reduce the overall manufacturing process costs.

It has become more commonplace in the past few years to employ paste inspection before components have been placed on the board. Here if defects are found, the board can be wiped clear and put back in to the assembly process with little cost or scrap. However, to work efficiently in this manner requires the stencil design to be performed in-house as opposed to sub-contracted outside to a third party. This allows the layout, pin/package and stencil aperture data to the reviewed and approved prior to commencing assembly. Also it allows the exact stencil data to then be available for programming the paste inspection equipment in a timely fashion.

It is also commonplace that many PCB assemblers need to merge the advantages of Boundary Scan Test (BST) with other forms of electrical test such as In-Circuit Test (ICT) or Flying Probe Test (FPT). The vPlan Test Engineering solution provides the ability to take the results of the BST analysis software of which nets require physical access and those that do not and use that as a constraint to the ICT and FPT test programming stages. Not only does this improve the test execution time of both platforms but it can also reduce the ICT fixture cost and also increase the fixture reliability.

It is here that a combined DFA, assembly, test and inspection process preparation solution can really provide significant benefit to a PCB assembler. Specifically, the Aberdeen Group found that test issues were reduced from 43% to 11% with the use of Valor DFM. Economies of scale can be achieved through single, complete data creation and analysis while leverage the layout and package data across all of the assembly process disciplines. The Valor Division’s vPlan product is the only product on the market today that combines the ability to provide integrated data preparation, DFA, assembly, documentation, stencil, test and inspection processes.

In my next blog I shall be discussing the role of manufacturer specific package data on the layout process. For more information on vPlan and vSure, please click on the following links:

http://www.mentor.com/pcb-manufacturing-assembly/

http://www.mentor.com/products/pcb-system-design/fabrication-assembly-test/vsure/

Mark Laing

Product Marketing Manager

Valor Division, Mentor Graphics Corporation

boundary scan, Design For Test, ICT, Flying Probe

More Blog Posts

Comments

No one has commented yet on this post. Be the first to comment below.

Add Your Comment

Please complete the following information to comment or sign in.

(Your email will not be published)

Archives

Tags

 
Online Chat