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PCB Manufacturing, Assembly & Test Blog

Posts tagged with 'Design For Test'

29 Jan, 2013

Mark Laing Hi there Next month on February 19th, 20th and 21st is the annual IPC Apex Convention in San Diego and there will be more than 400 exhibitors from 50 different countries represented at the show. Here are five reasons you should attend: 1. The Valor Division of Mentor Graphics will be exhibiting at booth 1227. So, you will be able to meet the U.S. sales team as well as some of the Product Line personnel … Read More

mixed vendor, AOI, Flying Probe, apex, ICT, IPC, bill of materials, BOM, approved vendor list, documentation, data preparation, Design For Test, vPlan, stencil, Sequence, programming, san diego, process

18 Dec, 2012

The Power of Auto-Generation

Posted by Mark Laing

Mark Laing Hi there I have talked about the Valor MSS unique capability to use the Valor Parts Library or VPL in multiple ways during PCB manufacturing. VPL data is manufacturer specific information about the actual component body and pin areas that can be used for multiple uses across DFM, Stencil, Documentation, SMT programming, test programming and inspection programming. I’d like to focus the specifics … Read More

Sequence, programming, AVL, mixed vendor, bill of materials, process, documentation, data preparation, Flying Probe, Design For Test, BOM, vPlan, stencil, VPL

27 Nov, 2012

Mark Laing Hi there I have talked to a number of users who are asking for capability to manage the Process Preparation needs of multiple locations around the world. I would like to hear from you on what requirements you consider important to this discussion. For example we have some customers running a single database across multiple locations allowing them to share data across all their facilities. One downside … Read More

programming, ICT, AVL, multi-site, data preparation, documentation, bill of materials, Flying Probe, BOM, Design For Test, database, server, testability, vPlan

20 Nov, 2012

Mark Laing Hi there It has been a few months since we launched the World Class Process Preparation Webinar including a video of an overall product demonstration. Over the past couple of months I have met with a number of people who implemented the Valor MSS Process Preparation solution and are achieving the efficiencies and improvements that we describe in the Webinar. Therefore I would like to provide you with … Read More

mixed vendor, AOI, Flying Probe, ICT, BOM, boundary scan, AVL, bill of materials, documentation, data preparation, Design For Test, vPlan, Planning, testability, VPL, stencil, programming, process

6 Nov, 2012

Mark Laing Hi there I have been posting comments on my blog now for a number of months. The topics have been based on the feedback and conversations I’ve had with many users of Process Engineering software, both Mentor Graphics and non-Mentor Graphics products, all around the world. Many of you have also taken the time to add comments on these postings which I really appreciate. I’d like to open up … Read More

mixed vendor, AOI, Flying Probe, ICT, BOM, boundary scan, AVL, bill of materials, documentation, data preparation, Design For Test, Planning, testability, vPlan, stencil, programming, process

2 Oct, 2012

Mark Laing Hi there I spent last week in the wonderful town of Zug about 45 minutes from Zurich in Switzerland. My European colleagues organized a two day seminar for over 60 of our Valor MSS Process Preparation customers at the Siemens facility in Zug. The agenda consisted of some Valor presentations, Valor demostrations of the upcoming software, presentations by actual users of the Process Preparation software … Read More

programming, AVL, process, AOI, data preparation, documentation, Flying Probe, bill of materials, ICT, BOM, Design For Test, vPlan, testability, VPL, stencil

18 Sep, 2012

Test and Inspection Strategies

Posted by Mark Laing

Mark Laing Hi there As a follow up to my posting last week on measuring test coverage, which you can read from the following link: http://www.mentor.com/pcb-manufacturing-assembly/blog/post/how-do-you-measure-test-coverage–77cbb106-851f-4f26-a548-4857098f23d4 I would like to hear from test and process engineers on what types of equipment form part of your test and inspection strategy. How do In-Circuit test … Read More

Design For Test, Flying Probe, AOI, testability, vPlan, ICT, data preparation, BOM, programming, boundary scan

12 Sep, 2012

How do you measure test coverage?

Posted by Mark Laing

Mark Laing Hi there With the Design For Test capability in Valor MSS Process Preparation, read details and see a video by clicking on the following link, we can analyze a board and determine the amount of physical test access to it. http://www.mentor.com/pcb-manufacturing-assembly/solutions/process-prep However the question of how to compare test coverage across multiple boards comes up from customers I talk with. … Read More

data preparation, Design For Test, ICT, Flying Probe

7 Aug, 2012

Mark Laing Hi there I have covered a number of areas of process engineering in this blog over the past few months and there is now an opportunity to see how these areas all come together next week in our Webinar titled “World Class Process Preparation”. We will be discussing a number of ways that the users of Valor MSS can streamline their process preparation tasks to make them more efficient and reduce … Read More

Planning, AOI, mixed vendor, BOM, data preparation, documentation, AVL, Flying Probe, bill of materials, ICT, Design For Test, process preparation, vPlan, Webinar, testability, stencil, programming, Sequence

17 Jul, 2012

Mark Laing Hi there One of the least efficient areas in PCB assembly concerns the creation and management of package data that will be consumed across the shop-floor. For example DFM processes rely on accurate package data to determine component to component spacing issues or using accurate pin terminus contact data to ensure that solder joints will form correctly. Accurate package data is critical for DFT analysis … Read More

programming, AOI, bill of materials, mixed vendor, process, data preparation, documentation, Design For Test, Flying Probe, ICT, BOM, VPL, vPlan, stencil, testability

10 Jul, 2012

Mark Laing Hi there Within the Valor MSS Process Preparation suite, we have the best DFA capability that exists in the market. There are a number of checks that are performed that are necessary for PCB assemblers to execute prior to starting a design in production. Being able to know if fiducials on the board are near similar pads or vias is important to ensure that placement and inspection equipment don’t … Read More

Flying Probe, bill of materials, testability, vPlan, ICT, Design For Test, BOM, data preparation

19 Jun, 2012

Testability versus Accessability

Posted by Mark Laing

Mark Laing Hi there Test Engineers are typically given the requirement to get 100% of nets probed at electrical test with the thinking that this delivers 100% testability. Unfortunately 100% accessibility is not the same as 100% testability. There are a number of reasons why this is not the case but here is a easy one. Typical boards contain integrated circuit (IC) components and power supplies. These power supplies … Read More

programming, data preparation, Design For Test, ICT, testability, Flying Probe

12 Jun, 2012

Mark Laing Hi there When providing accurate Design For Test (DFT) feedback to board designers, individual targets are usually inaccessible for a number of reasons. However, most DFT products only report the first reason a target is inaccessible. So this limited feedback is provided to the designer who corrects that single problem, only to find that when the analysis is run again on the new layout another reason … Read More

data preparation, Flying Probe, programming, ICT, Design For Test, vPlan

6 Jun, 2012

Hot and humid in Israel

Posted by Mark Laing

Mark Laing Dear all It has been a few months but this week I am out at the Mentor Graphics office in Yavne, Israel. I have been working with the R&D team out here on the upcoming versions of our Process Engineering solutions. I certainly appreciate people taking the time to respond to my blog last week on stencil apertures. The new area ratio report as discussed in last week’s blog will be part of the … Read More

Enhancement, documentation, Flying Probe, VPL, vPlan, programming, BOM, AOI, stencil, data preparation, Design For Test, Planning

24 Sep, 2011

Mark Laing Another area I discussed in my recent article for PCB007 was with Design For Test or DFT. Ensuring that accurate test or inspection techniques have been catered for before a layout is signed off will ensure that any assembly or component issues will be found as early as possible in the manufacturing process. For each additional step during the manufacturing process it is estimated that the cost of corrective … Read More

boundary scan, Design For Test, ICT, Flying Probe

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