Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A point-to-point differential pair doesn’t mean the layout is dirt easy; it means the design challenges have transformed. Keeping in mind that the board is part of the electrical design, we will outline the important high-speed considerations and efficient ways to account for them in high-speed PCB layouts. The approach to board design must start with power and layer planning, include high speed specific rules, and pull in a couple high-speed-specific design disciplines, such as feature automation and signal integrity (SI) simulation.