We go through great pains to ensure that our analysis tools give highly accurate answers in the most efficient manner possible. That requires accurate field solving – in both 2 dimensions and 3 dimensions, as appropriate – as well as accurate simulation. Accurate simulation includes simulation of S-parameters in the time domain, which requires appropriate handling of causality and passivity issues, proper concatenation of multiple S-parameters, and the avoidance of common pitfalls from brute-force methods like convolution (we use complex pole-fitting instead, which is accurate and efficient). It also means appropriately handling all determinsitic and random jitter sources by utlizing worst-case bit sequences to accurately predict BER down to 10^-18 and beyond. All of this becomes crucial at multi-GBs SERDES speeds. An example of SERDES simulation/measurement correlation can be found in the following article: http://electronicdesign.com/what-s-difference-between/what-s-difference-between-simulation-and-measurement
It is important to make sure that all of your inputs into the simulation are accurate. That starts with something as simple as getting the board stackup and trace widths to match what is actually manufactured – take a look at the references at the end of the article above (or some of my previous blogs) for more info. For SERDES speeds specifically, that means making sure any models used, like SPICE and S-parameters, have the the appropriate bandwidth, and that all the pieces of the channel have been solved with the appropriate field solver. Even for PI, it is important to make sure that capacitor ESL is appropriately understood and the correct method of modeling ESL is used, as this can have a dramatic effect on the results of a PI analysis.
If you take the time to make sure you are feeding HyperLynx the right information, it will give you the answers you seek about the true performance of your design.